Intel Xeon 7130N LF80550KF0878M Data Sheet

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A[39:3]#

I/O

A[39:3]# (Address) define a 2

40

-byte physical memory address space. In sub-phase 1 of the address 

phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit 
transaction type information. These signals must connect the appropriate pins of all agents on the 
Dual-Core Intel Xeon processor 7000 series FSB. A[39:3]# are protected by parity signals AP[1:0]#. 
A[39:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#.

On the active-to-inactive transition of RESET#, the processors sample a subset of the A[39:3]# pins 
to determine their power-on configuration. See 

.

A20M#

I

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before 
looking up a line in any internal cache and before driving a read/write transaction on the bus. 
Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. 
Assertion of A20M# is only supported in real mode.

A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O 
write instruction, it must be valid 6 clks before the I/O write’s response. 

ADS#

I/O

ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[39:3]# 
and transaction request type on REQ[4:0]# pins. All bus agents observe the ADS# activation to begin 
parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match 
operations associated with the new transaction. This signal must connect the appropriate pins on all 
Dual-Core Intel Xeon processor 7000 series FSB agents.

ADSTB[1:0]#

I/O

Address strobes are used to latch A[39:3]# and REQ[4:0]# on their rising and falling edge.

AP[1:0]#

I/O

AP[1:0]# (Address Parity) are driven by the requestor one common clock after ADS#, A[39:3]#, 
REQ[4:0]# are driven. A correct parity signal is electrically high if an even number of covered signals 
are electrically low and electrically low if an odd number of covered signals are electrically low. This 
allows parity to be electrically high when all the covered signals are electrically high. AP[1:0]# should 
connect the appropriate pins of all Dual-Core Intel Xeon processor 7000 series FSB agents. The 
following table defines the coverage for these signals.

BCLK[1:0]

I

The differential bus clock pair BCLK[1:0] determines the bus frequency. All processor FSB agents 
must receive these signals to drive their outputs and latch their inputs.

All external timing parameters are specified with respect to the rising edge of BCLK0 crossing the 
falling edge of BCLK1.

BINIT#

I/O

BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents. If used, BINIT# 
must connect the appropriate pins of all such agents. If the BINIT# driver is enabled, BINIT# is 
asserted to signal any bus condition that prevents reliable future operation.

If BINIT# observation is enabled during power-on configuration (see 

) and BINIT# is 

sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state 
machines. The bus agents do not reset their I/O Queue (IOQ) and transaction tracking state 
machines upon observation of BINIT# assertion. Once the BINIT# assertion has been observed, the 
bus agents will re-arbitrate for the FSB and attempt completion of their bus queue and IOQ entries.

If BINIT# observation is enabled during power on configuration, a central agent may handle an 
assertion of BINIT# as appropriate to the error handling architecture of the system.

A[39:24]#

AP0#

AP1#

A[23:3]#

AP1#

AP0#

REQ[4:0]#

AP1#

AP0#