Intel Xeon 7130N LF80550KF0878M Data Sheet

63

ODTEN

I

ODTEN (On-die termination enable) should be connected to V

TT

 through a resistor to enable on-die 

termination for end bus agents. For middle bus agents, pull this signal down via a resistor to ground 
to disable on-die termination. Whenever ODTEN is high, on-die termination will be active, regardless 
of other states of the bus.

PROCHOT#

O

The assertion of PROCHOT# (processor hot) indicates that the processor die temperature has 
reached its thermal limit. See 

 for more details.

PROCTYPE

O

PROCTYPE is used to identify when the Dual-Core Intel Xeon processor 7000 series is installed. 
This pin should be used to toggle logic needed for the Dual-Core Intel Xeon processor 7000 
series/64-bit Intel

®

 Xeon

®

 Processor MP with up to 8MB L3 Cache or 64-bit Intel

®

 Xeon

®

 Processor 

MP with 1MB L2 Cache. The pin is left floating on the Dual-Core Intel

®

Xeon

®

 Processor 7000 Series 

package while on the 64-bit Intel

®

 Xeon

®

 Processor MP with up to 8MB L3 Cache packages this pin 

connects to V

SS

PWRGOOD

I

PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean indication 
that all Dual-Core Intel Xeon processor 7000 series clocks and power supplies are stable and within 
their specifications. “Clean” implies that the signal will remain low (capable of sinking leakage 
current), without glitches, from the time that the power supplies are turned on until they come within 
specification. The signal must then transition monotonically to a high state. 

The PWRGOOD signal must be supplied to the processor. This signal is used to protect internal 
circuits against voltage sequencing issues. It should be driven high throughout boundary scan 
operation.

REQ[4:0]#

I/O

REQ[4:0]# (Request Command) must connect the appropriate pins of all processor FSB agents. 
They are asserted by the current bus owner to define the currently active transaction type. These 
signals are source synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details 
on parity checking of these signals.

RESET#

I

Asserting the RESET# signal resets all processors to known states and invalidates their internal 
caches without writing back any of their contents. For a power-on Reset, RESET# must stay active 
for at least 1 ms after V

CC

 and BCLK have reached their specified levels. On observing active 

RESET#, all FSB agents will deassert their outputs within two clocks. RESET# must not be kept 
asserted for more than 10 ms after PWRGOOD is asserted.

A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on 
configuration. These configuration options are described in 

RS[2:0]#

I

RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion 
of the current transaction), and must connect the appropriate pins of all processor FSB agents.

RSP#

I

RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the 
current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity 
protection. It must connect to the appropriate pins of all processor FSB agents.

A correct parity signal is electrically high if an even number of covered signals are electrically low 
and electrically low if an odd number of covered signals are electrically low. If RS[2:0]# are all 
electrically high, RSP# is also electrically high, since this indicates it is not being driven by any agent 
guaranteeing correct parity.

SKTOCC#

O

SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate that the processor 
is present. There is no connection to the processor silicon for this signal.

SM_ALERT#

O

SM_ALERT# (SMBus Alert) is an asynchronous interrupt line associated with the SMBus Thermal 
Sensor device. It is an open-drain output and the processor includes a 10 k

Ω pull-up resistor to 

SM_VCC for this signal. For more information on the usage of the SM_ALERT# pin, see 

SM_CLK

I/O

The SM_CLK (SMBus Clock) signal is an input clock to the system management logic which is 
required for operation of the system management features of the Dual-Core Intel Xeon processor 
7000 series. This clock is driven by the SMBus controller and is asynchronous to other clocks in the 
processor.The processor includes a 10 k

Ω pull-up resistor to SM_VCC for this signal.

SM_DAT

I/O

The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal provides the 
single-bit mechanism for transferring data between SMBus devices. The processor includes a 10 k

Ω 

pull-up resistor to SM_VCC for this signal.