Intel X3450 BV80605001911AQ User Manual
Product codes
BV80605001911AQ
Introduction
12
Datasheet, Volume 1
System memory features include:
• Data burst length of eight for all memory organization modes
• 64-bit wide channels
• DDR3 I/O Voltage of 1.5 V
• Maximum memory bandwidth of 10.6 GB/s in single-channel mode or 21 GB/s in
• 64-bit wide channels
• DDR3 I/O Voltage of 1.5 V
• Maximum memory bandwidth of 10.6 GB/s in single-channel mode or 21 GB/s in
dual-channel mode assuming DDR3 1333 MT/s
• 1-Gb and 2-Gb DDR3 DRAM technologies are supported.
• Using 2-Gb device technologies, the largest memory capacity possible is 16 GB for
• Using 2-Gb device technologies, the largest memory capacity possible is 16 GB for
UDIMMs (assuming Dual Channel Mode with a four dual rank unbuffered, non-ECC
DIMM memory configuration), and 32 GB for RDIMMs (assuming
DIMM memory configuration), and 32 GB for RDIMMs (assuming
Dual Channel
Mode with a four quad-rank registered DIMM memory configuration
)
• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank
devices)
• Command launch modes of 1n/2n
• Intel
• Intel
®
Fast Memory Access (Intel
®
FMA)
— Just-in-Time Command Scheduling
— Command Overlap
— Out-of-Order Scheduling
— Command Overlap
— Out-of-Order Scheduling
1.2.2
PCI Express*
• The processor PCI Express* port(s) are fully-compliant with the PCI Express Base
Specification, Revision 2.0.
• Intel
®
Xeon
®
processor 3400 series with the Intel
®
3450 Chipset supports:
— One 16-lane PCI Express port intended for graphics attach.
— Two 8-lane PCI Express ports for graphics or I/O.
— Two 8-lane PCI Express ports for graphics or I/O.
• Intel
®
Xeon
®
processor 3400 series with the Intel 3420 Chipset supports:
— One 16-lane PCI Express port intended for graphics or I/O.
— Two 8-lane PCI Express ports intended for I/O.
— Four 4-lane PCI Express ports intended for I/O.
— Two 8-lane PCI Express ports intended for I/O.
— Four 4-lane PCI Express ports intended for I/O.
• Intel
®
Xeon
®
processor 3400 series with the Intel 3400 Chipset supports:
— Two 8-lane PCI Express ports intended for I/O.
— Four 4-lane PCI Express ports intended for I/O.
— Four 4-lane PCI Express ports intended for I/O.
• PCI Express port 0 is mapped to PCI Device 3.
• PCI Express port 1 is mapped to PCI Device 5.
• The port may negotiate down to narrower widths.
• PCI Express port 1 is mapped to PCI Device 5.
• The port may negotiate down to narrower widths.
— Support for x16/x8/x4/x1 widths for a single PCI Express mode.
• 2.5 GT/s and 5.0 GT/s PCI Express frequencies are supported.
• Either port can be configured independently as 2.5 GT/s or 5.0 GT/s.
• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
• Either port can be configured independently as 2.5 GT/s or 5.0 GT/s.
• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface.
This also does not account for packet overhead and link maintenance.
This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s for x16.
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).