Intel X3450 BV80605001911AQ User Manual
Product codes
BV80605001911AQ
Datasheet, Volume 1
5
Electrical Specifications ........................................................................................... 61
7.1
7.1
Voltage Identification (VID) .......................................................................... 62
7.10 Platform Environmental Control Interface (PECI) DC Specifications........................... 77
7.10.1 DC Characteristics .................................................................................. 77
7.10.2 Input Device Hysteresis .......................................................................... 78
7.10.2 Input Device Hysteresis .......................................................................... 78
Processor Land and Signal Information ................................................................... 79
8.1
8.1
Figures
®
Xeon
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Processor 3400 Series Platform Diagram ................................................. 10
®
Flex Memory Technology Operation................................................................... 22
2-2 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes .................. 23
2-3 PCI Express* Layering Diagram ................................................................................. 25
2-4 Packet Flow through the Layers ................................................................................. 26
2-5 PCI Express* Related Register Structures in Processor ................................................. 27
4-1 Idle Power Management Breakdown of the Processor Cores ........................................... 37
4-2 Thread and Core C-State Entry and Exit ...................................................................... 38
4-3 Package C-State Entry and Exit.................................................................................. 42
7-1 V
2-3 PCI Express* Layering Diagram ................................................................................. 25
2-4 Packet Flow through the Layers ................................................................................. 26
2-5 PCI Express* Related Register Structures in Processor ................................................. 27
4-1 Idle Power Management Breakdown of the Processor Cores ........................................... 37
4-2 Thread and Core C-State Entry and Exit ...................................................................... 38
4-3 Package C-State Entry and Exit.................................................................................. 42
7-1 V
Static and Transient Tolerance Loadlines ............................................................... 73
7-2 Input Device Hysteresis ............................................................................................ 78
8-1 Socket Pinmap (Top View, Upper-Left Quadrant) .......................................................... 80
8-2 Socket Pinmap (Top View, Upper-Right Quadrant) ........................................................ 81
8-3 Socket Pinmap (Top View, Lower-Left Quadrant) .......................................................... 82
8-4 Socket Pinmap (Top View, Lower-Right Quadrant) ........................................................ 83
8-1 Socket Pinmap (Top View, Upper-Left Quadrant) .......................................................... 80
8-2 Socket Pinmap (Top View, Upper-Right Quadrant) ........................................................ 81
8-3 Socket Pinmap (Top View, Lower-Left Quadrant) .......................................................... 82
8-4 Socket Pinmap (Top View, Lower-Right Quadrant) ........................................................ 83
Tables
Xeon
®
Processor 3400 Series Supported Memory Summary................................ 11
1-2 Related Documents ................................................................................................. 17
2-1 Supported DIMM Module Configurations ..................................................................... 20
2-2 DDR3 System Memory Timing Support ..................................................................... 21
2-3 System Memory Pre-Charge Power Down Support ....................................................... 24
2-4 Processor Reference Clock Requirements ................................................................... 29
4-1 Processor Core/Package State Support ...................................................................... 35
4-2 G, S, and C State Combinations................................................................................ 36
4-3 Coordination of Thread Power States at the Core Level ................................................ 38
4-4 P_LVLx to MWAIT Conversion ................................................................................... 39
4-5 Coordination of Core Power States at the Package Level............................................... 41
4-6 Targeted Memory State Conditions............................................................................ 44
6-1 Signal Description Buffer Types ................................................................................ 49
6-2 Memory Channel A.................................................................................................. 50
6-3 Memory Channel B.................................................................................................. 51
6-4 Memory Reference and Compensation ....................................................................... 52
2-1 Supported DIMM Module Configurations ..................................................................... 20
2-2 DDR3 System Memory Timing Support ..................................................................... 21
2-3 System Memory Pre-Charge Power Down Support ....................................................... 24
2-4 Processor Reference Clock Requirements ................................................................... 29
4-1 Processor Core/Package State Support ...................................................................... 35
4-2 G, S, and C State Combinations................................................................................ 36
4-3 Coordination of Thread Power States at the Core Level ................................................ 38
4-4 P_LVLx to MWAIT Conversion ................................................................................... 39
4-5 Coordination of Core Power States at the Package Level............................................... 41
4-6 Targeted Memory State Conditions............................................................................ 44
6-1 Signal Description Buffer Types ................................................................................ 49
6-2 Memory Channel A.................................................................................................. 50
6-3 Memory Channel B.................................................................................................. 51
6-4 Memory Reference and Compensation ....................................................................... 52