Intel 9110N NE80567KE025003 User Manual
Product codes
NE80567KE025003
System Management Bus Interface
104
Intel
®
Itanium
®
Processor 9300 Series Datasheet
6.2.2
Scratch EEPROM
Intel Itanium processor 9300 series supports a Scratch EEPROM section, which may be
used for other data at the system vendor’s discretion. The data in this EEPROM, once
programmed, can be write-protected by asserting the active-high SM_WP signal. This
signal has a weak pull-down (10 k) to allow the EEPROM to be programmed in
used for other data at the system vendor’s discretion. The data in this EEPROM, once
programmed, can be write-protected by asserting the active-high SM_WP signal. This
signal has a weak pull-down (10 k) to allow the EEPROM to be programmed in
systems with no implementation of this signal. The Scratch EEPROM resides in the
upper half of the memory component (addresses 80 - FFh). The lower half comprises
the Processor Information ROM (addresses 00 - 7Fh), which is permanently write-
protected.
upper half of the memory component (addresses 80 - FFh). The lower half comprises
the Processor Information ROM (addresses 00 - 7Fh), which is permanently write-
protected.
6.2.3
PIROM and Scratch EEPROM Supported SMBus
Transactions
The PIROM responds to two SMBus packet types: Read Byte and Write Byte. However,
since the PIROM is write-protected, it will acknowledge a Write Byte command but
ignores the data. The Scratch EEPROM responds to Read Byte and Write Byte
commands.
since the PIROM is write-protected, it will acknowledge a Write Byte command but
ignores the data. The Scratch EEPROM responds to Read Byte and Write Byte
commands.
illustrates the Read Byte command.
illustrates the
Write Byte command.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘A’ represents
an acknowledge (ACK), and ‘///’ represents a negative acknowledge (NACK). The
shaded bits are transmitted by the PIROM or Scratch EEPROM, and the bits that aren’t
shaded are transmitted by the SMBus host controller. In the tables, the data addresses
indicate 8 bits.
an acknowledge (ACK), and ‘///’ represents a negative acknowledge (NACK). The
shaded bits are transmitted by the PIROM or Scratch EEPROM, and the bits that aren’t
shaded are transmitted by the SMBus host controller. In the tables, the data addresses
indicate 8 bits.
The SMBus host controller should transmit 8 bits with the most significant bit indicating
which section of the EEPROM is to be addressed: the PIROM (MSB = 0) or the Scratch
EEPROM (MSB = 1).
which section of the EEPROM is to be addressed: the PIROM (MSB = 0) or the Scratch
EEPROM (MSB = 1).
120
78h
Package Feature Flags
hex
all other are reserved
Bit[3] = THERMALERT_N
threshold values present
Bit[2] = SCRATCH EEPROM
present
Bit[1] = Core VID present
where a 1 indicates valid
data
Flag = 0x000E
78h = 0x0E
79h = 0x00
79h = 0x00
121
79h
122
7Ah
RESERVED
hex
Reserved for future use
7Ah = 0x00
123
7Bh
Number of Devices in TAP
Chain
Chain
hex
Bits [7:4] Number Devices
in processor TAP chain
Bits [3:0] Reserved
in processor TAP chain
Bits [3:0] Reserved
5 devices for TKW = 0x50
124
7Ch
Checksum
hex
Add up by byte and take
2's compliment
2's compliment
Other
125
7Dh
RESERVED
hex
Reserved for future use
7Dh = 0x00
7Eh = 0x00
7Fh = 0x00
7Fh = 0x00
126
7Eh
127
7Fh
Table 6-1.
Processor Information ROM Data (Sheet 6 of 6)
Sec #
Offset
Field Name
Data Type
Description
Example