Intel 9110N NE80567KE025003 User Manual
Product codes
NE80567KE025003
Intel
®
Itanium
®
Processor 9300 Series Datasheet
117
Intel Itanium Processor 9300 Series Signal Definitions
FLASHROM_CFG[2:0]
I
These are input signals to the processor that would initialize and map the Flash
ROM upon reset. After reset is deasserted this input would be ignored by the
processor logic. These pins are sampled during all resets except warm-logic reset.
FLASHROM_CLK
O
The Flash ROM clock.
FLASHROM_CS[3:0]_N
O
Flash ROM chip selects. Up to four separate flash ROM parts may be used.
FLASHROM_DATI
I
Serial Data Input (from ROM(s) to processor).
FLASHROM_DATO
O
Serial Data Output (from processor to ROM(s))
FLASHROM_WP_N
O
Flash ROM write-protect.
FORCEPR_N
I
When logic 0, forces processor power reduction through the FOXTON controller.
Refer to Intel® Itanium® 9300 Series External Design Specification for detailed
Refer to Intel® Itanium® 9300 Series External Design Specification for detailed
signal description.
LRGSCLSYS
I
The header mode is selected by the LRGSCLSYS strapping pin value sampled only
during COLD reset. LRGSCLSYS, when tied to 1.1 V using a 50 ohm resistor, puts
the processor in extended header mode, and LRGSCLSYS, when tied to GND, puts
the the processor in standard header mode.
MEM_THROTTLE_L
I
When this pin is asserted, the internal memory controllers throttle the memory
command issue rate to a configurable fraction of the nominal command rate
settings.
PIR_SCL
I
(Processor Information ROM Serial Clock): The PIR_SCL input clock is used to clock
data into and out of the on package PIROM device. This signal applies to the
EEPROM, which is composed of the PIROM and the OEM Scratch PAD.
PIR_SDA
I/O
(Processor Information ROM Serial Data): The PIR_SDA pin is a bidirectional signal
for serial data transfer. This signal applies to the EEPROM, which is composed of the
PIROM and the OEM Scratch PAD
PIR_A0, PIR_A1
I
(Processor Information ROM Address[0:1]): The PIR_A[0:1] pins are used as the
PIROM memory address selection signals. This bus applies to the EEPROM, which is
composed of the PIROM and the OEM Scratch PAD
SM_WP
I
WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch
EEPROM is write-protected when this input is pulled high to VCC33_SM.
PRBMODE_REQ_N
I
Input from Extended Debug Port (XDP) to make a probe mode request.
PRBMODE_RDY_N
O
Output to XDP to acknowledge probe mode request.
PROCHOT_N
O
The assertion of PROCHOT_N (processor hot) indicates that the processor die
temperature has reached its thermal limit.
PROCTYPE
O
PROCTYPE output informs the platform the processor type. PROCTYPE is tied to VSS
internally to indicate the Intel® Itanium® processor 9300 series. This pin does not
require a platfrom pull-up or pull-down.
PWRGOOD
I
The processor requires this signal to be a clean indication that all the processor
clocks and power supplies are stable and within their specifications. “Clean” implies
that the signal will remain low (capable of sinking leakage current), without
glitches, from the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor. This signal is used to
The PWRGOOD signal must be supplied to the processor. This signal is used to
protect internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
RESET_N
I
Asserting the RESET_N signal resets the processor to a known state and invalidates
its internal caches without writing back any of their contents. BOOTMODE[0:1]
signals are sampled during all RESET_N assertions for selecting appropriate
BOOTMODE.
RSVD
These pins are reserved and should be left unconnected.
SKTID[2:0]
I
Socket ID strapping pins.
To pull any of these inputs high, they should be strapped
to VCCIO, and to pull them low, they should be strapped to VSS. SKTID[2:0]
partially determine the node address.
Table 7-1.
Signal Definitions Intel Itanium Processor 9300 Series
(Sheet 5 of 8)
Name
Type
Description