Intel 9110N NE80567KE025003 User Manual

18

1.

Parameter value at full Intel QPI Refclk

2.

Stagger offset = 0xF

3.

See 

4.

The termination small signal resistance; tolerance over the entire signalling voltage range shall not exceed ±5 ohms

5.

Requires Matlab script 

6.

Refer to Intel QuickPath Interconnect (Intel QPI) - Electrical Specifications for calculation of this value. Note that UI to UI 

definition is used herein, where the value of UI-UI DCD = 2*UI DCD.

7.

See 

8.

Applies to Vtx-diff-pp-pin

9.

Peak-to-peak value of the ripple

T

INBAND_RESET_SE

N

SE

Time taken by inband reset detector to sense 

Inband Reset

8k

256k

UI

T

CLK_DET

Time taken by clock detector to observe clock 

stability

8k

256k

UI

T

SYSCLK

-T

X

-V

ARIABILITY

Phase variability between reference Clk (at Tx 

input) and Tx output.

500

ps

TX

EQ-BOOST

Voltage ratio between the cursor and the 

post-cursor when transmitting successive 

ones

0

25

dB

3

V

T

X

-

CM

-

PIN

Transmitter data or clock common mode level 

23

27

%

V

T

X

-

CM

-

RIPPLE

-

PIN

Transmitter data or clock common mode 

ripple

0

14

%

8,9

TX

DUTY

-

CYCLE

-

PIN

Transmitter clock or data duty cycle at the 

pin. Transmit duty cycle at the pin, defined as 

UI to UI jitter as specified by the Intel QPI 

Electrical Specification, Rev 1.0.

-0.076

0.076

UI-UI

6

T

T

X

-

DATA

-

CLK

-

SKEW

-

PIN

Delay of any data lane relative to clock lane, 

as measured at Tx output 

-0.5

0.5

UI

1,2

TX

ACC

-

JIT

-N_UI-1E-9

Peak-to-peak accumulated jitter out of any TX 

data or clock over 0<= n <= N UI where 

N=12, measured with 1E-9 probability. 

0

0.18

UI

5

TX

JIT

U

I

-UI-1E-9

PIN

Transmitter clock or data UI-UI jitter at 1E-9 

probability. 

0

0.17

UI

5

RL

TX-DIFF

Transmitter Differential return loss from 

50MHz to 2GHz

-10

dB

7

RL

TX-DIFF

Transmitter Differential return loss from
2GHz to 4GHz

-6

dB

7

R

RX

RX termination resistance

37.4

47.6



3

T

Rx-data-clk-skew-pin

Delay of any data lane relative to the clock lane, as 

measured at the end of Tx+ channel. This parameter is 

a collective sum of effects of data clock mismatches in 

Tx and on the medium connecting Tx and Rx. 

-0.5

3.5

UI

2

T

Rx-data-clk-skew-pin

Delay of any data lane relative to the clock lane, as 

measured at the end of Tx+ channel. This parameter is 

a collective sum of effects of data clock mismatches in 

Tx and on the medium connecting Tx and Rx. 

0.48

0.52

UI

1

RL

RX-DIFF

Receiver differential return loss from 50 MHz to 2 GHz

-10

dB

6

RL

RX-DIFF

Receiver differential return loss from 2GHz to 4GHz

-6

dB

6