Intel D525 AU80610006225AA User Manual
Product codes
AU80610006225AA
Datasheet
19
Signal Description
2.2
System Memory Interface
PREQ#
PREQ# is used by debug tools to request debug
operation of the processor.
operation of the processor.
I
GTL+
DPRSTP#
DPRSTP# when asserted on the platform causes the
processor to transition from Deep Sleep State to the
Deeper Sleep State. To return to the Deep Sleep
State, DPRSTP# must be deasserted. DPRSTP# is
driven by the chipset. This function is not supported
for Intel Atom Processor D400 and D500 Series.
processor to transition from Deep Sleep State to the
Deeper Sleep State. To return to the Deep Sleep
State, DPRSTP# must be deasserted. DPRSTP# is
driven by the chipset. This function is not supported
for Intel Atom Processor D400 and D500 Series.
I
Core
CMOS
DPSLP#
DPSLP# when asserted on the platform causes the
processor to transition from the Sleep State to the
Deep Sleep State. To return to the Sleep State,
DPSLP# must be de-asserted. DPSLP# is driven by
the chipset. This function is not supported for Intel
Atom Processor D400 and D500 Series.
processor to transition from the Sleep State to the
Deep Sleep State. To return to the Sleep State,
DPSLP# must be de-asserted. DPSLP# is driven by
the chipset. This function is not supported for Intel
Atom Processor D400 and D500 Series.
I
Core
CMOS
Table 2-5. Memory Channel A
Signal Name
Description Direction
Type
DDR_A_CK_5:0
SDRAM Differential Clock: (3 per DIMM)
O
SSTL-1.8
DDR_A_CKB_5:0
SDRAM Inverted Differential Clock: (3 per DIMM)
O
SSTL-1.8
DDR_A_CSB_3:0
Chip Select: (1 per Rank)
O
SSTL-1.8
DDR_A_CKE_3:0
Clock Enable: (power management - 1 per Rank)
O
SSTL-1.8
DDR_A_MA_14:0
Multiplexed Address
O
SSTL-1.8
DDR_A_BS_2:0
Bank Select
O
SSTL-1.8
DDR_A_RASB
RAS Control Signal
O
SSTL-1.8
DDR_A_CASB
CAS Control Signal
O
SSTL-1.8
DDR_A_WEB
Write Enable Control Signal
O
SSTL-1.8
DDR_A_DQ_63:0
Data Lines
I/O
SSTL-1.8
2x
DDR_A_DM_7:0
Data Mask: These signals are used to mask individual
bytes of data in the case of a partial write, and to interrupt
burst writes
bytes of data in the case of a partial write, and to interrupt
burst writes
O
SSTL-1.8
2x
DDR_A_DQS_7:0
Data Strobes
I/O
SSTL-1.8
2x
DDR_A_DQSB_7:0
Data Strobe Complements (DDR2)
I/O
SSTL-1.8
2x
DDR_A_ODT_3:0
On Die Termination: Active Termination Control (DDR2)
O
SSTL-1.8
2x
Table 2-4. CPU Legacy Signal
Signal Name
Description
Direction
Type