Intel D525 AU80610006225AA User Manual
Product codes
AU80610006225AA
Datasheet
37
Electrical Specifications
4
Electrical Specifications
This chapter contains signal group descriptions, absolute maximum ratings, voltage
identification and power sequencing. The chapter also includes DC and AC
specifications, including timing diagrams.
identification and power sequencing. The chapter also includes DC and AC
specifications, including timing diagrams.
4.1
Power and Ground Balls
The processor has V
CC*
and V
SS
(ground) inputs for on-chip power distribution. All
power balls must be connected to their respective processor power planes, while all V
SS
balls must be connected to the system ground plane. Use of multiple power and ground
planes is recommended to reduce I*R drop. The V
planes is recommended to reduce I*R drop. The V
CC
balls must be supplied with the
voltage determined by the processor Voltage IDentification (VID) signals.
4.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low and full-power states. This
may cause voltages on power planes to sag below their minimum values, if bulk
decoupling is not adequate. Larger bulk storage (C
capable of generating large current swings between low and full-power states. This
may cause voltages on power planes to sag below their minimum values, if bulk
decoupling is not adequate. Larger bulk storage (C
BULK
), such as electrolytic capacitors,
supply current during longer lasting changes in current demand (for example, coming
out of an idle condition). Similarly, capacitors act as a storage well for current when
entering an idle condition from a running condition. To keep voltages within
specification, output decoupling must be properly designed.
out of an idle condition). Similarly, capacitors act as a storage well for current when
entering an idle condition from a running condition. To keep voltages within
specification, output decoupling must be properly designed.
Caution:
Design the board to ensure that the voltage provided to the processor remains within
the specifications. Failure to do so can result in timing violations or reduced lifetime of
the processor.
the specifications. Failure to do so can result in timing violations or reduced lifetime of
the processor.
4.2.1
Voltage Rail Decoupling
The voltage regulator solution needs to provide:
•
bulk capacitance with low effective series resistance (ESR).
•
a low path impedance from the regulator to the CPU.
•
bulk decoupling to compensate for large current swings generated during power-
on, or low-power idle state entry/exit.
on, or low-power idle state entry/exit.
The power delivery solution must ensure that the voltage and current specifications are
met, as defined in
met, as defined in
. For further information regarding power delivery,
decoupling, and layout guidelines refer to the appropriate platform design guide.