Intel 9150N NE80567KE025015 User Manual
Product codes
NE80567KE025015
Introduction
10
Intel
®
Itanium
®
Processor 9300 Series Datasheet
Itanium
®
Architecture Software Developer’s Manual, Volume 2: System Architecture,
describes PAL. Platforms must provide access to the firmware address space and PAL at
reset to allow the processors to initialize.
reset to allow the processors to initialize.
The System Abstraction Layer (SAL) firmware contains platform-specific firmware to
initialize the platform, boot to an operating system, and provide runtime functionality.
Further information about SAL is available in the Intel
initialize the platform, boot to an operating system, and provide runtime functionality.
Further information about SAL is available in the Intel
®
Itanium
®
Processor Family
System Abstraction Layer Specification.
1.3
Mixing Processors of Different Frequencies and
Cache Sizes
All Intel Itanium processor 9300 series in the same system partition are required to
have the same cache size (24 MB, 20 MB, 16 MB or 10 MB) and identical core
frequency. Mixing components of different core frequencies and cache sizes is not
supported and has not been validated by Intel. Operating system support for
multiprocessing with mixed components should also be considered.
have the same cache size (24 MB, 20 MB, 16 MB or 10 MB) and identical core
frequency. Mixing components of different core frequencies and cache sizes is not
supported and has not been validated by Intel. Operating system support for
multiprocessing with mixed components should also be considered.
While Intel has done nothing to specifically prevent processors within a multiprocessor
environment from operating at differing frequencies and differing cache sizes, there
may be uncharacterized errata that exist in such configurations. Customers would be
fully responsible for validation of system configurations with mixed components other
than the supported configurations described above.
environment from operating at differing frequencies and differing cache sizes, there
may be uncharacterized errata that exist in such configurations. Customers would be
fully responsible for validation of system configurations with mixed components other
than the supported configurations described above.
1.4
Terminology
In this document, “the processor” refers to the Intel Itanium processor 9300 series,
unless otherwise indicated.
unless otherwise indicated.
An ‘_N’ notation after a signal name refers to an active low signal. This means that a
signal is in the active state (based on the name of the signal) when driven to a low
level. For example, when RESET_N is low, a processor reset has been requested. When
NMI is high, a non-maskable interrupt has occurred. In the case of lines where the
name does not imply an active state but describes part of a binary sequence (such as
address or data), the ‘_N’ notation implies that the signal is inverted. For example,
D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D [3:0] _N = ‘LHLH’ also refers to a hex ‘A’ (H =
High logic level, L = Low logic level).
signal is in the active state (based on the name of the signal) when driven to a low
level. For example, when RESET_N is low, a processor reset has been requested. When
NMI is high, a non-maskable interrupt has occurred. In the case of lines where the
name does not imply an active state but describes part of a binary sequence (such as
address or data), the ‘_N’ notation implies that the signal is inverted. For example,
D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D [3:0] _N = ‘LHLH’ also refers to a hex ‘A’ (H =
High logic level, L = Low logic level).
A signal name has all capitalized letters, for example, VCTERM.
A symbol referring to a voltage level, current level, or a time value carries a plain
subscript, for example, Vccio, or a capitalized abbreviated subscript, for example, TCO.
subscript, for example, Vccio, or a capitalized abbreviated subscript, for example, TCO.
1.5
State of Data
The data contained in this document is subject to change. It is the best information
that Intel is able to provide at the publication date of this document.
that Intel is able to provide at the publication date of this document.