Intel 9150N NE80567KE025015 User Manual

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SMBCLK

I/O

The SMBus Clock (SMBCLK) signal is an input clock to the system management 

logic which is required for operation of the system management features of the 

Intel Itanium processor 9300 series. This clock is driven by the SMBus controller 

and is asynchronous to other clocks in the processor. This is an open drain signal. 

Intel Itanium processor 9300 series is Slave only.

SMBDAT

I/O

The SMBus Data (SMBDAT) signal is the data signal for the SMBus. This signal 

provides the single-bit mechanism for transferring data between SMBus devices. 

This is an open drain signal. Intel Itanium processor 9300 series is Slave only.

SPDCLK

I/O

This is a bi-directional clock signal between the processor, DRAM SPD registers and 

external components on the board. This is an open drain signal. The processor is 

Master only; refer to Intel

 9300 Series External Design Specification for 

limitations.

SPDDAT

I/O

This is a bi-directional data signal between the processor, DRAM SPD registers and 

external components on the board. This is an open drain signal. Intel Itanium 

processor 9300 series is Master only; refer to Intel

Series External Design Specification for limitations.

SYSCLK/SYSCLK_N

I

The differential clock pair SYSCLK/SYSCLK_N provides the fundamental clock 

source for the processor. All processor link agents must receive these signals to 

drive their outputs and latch their inputs. All external timing parameters are 

specified with respect to the rising edge of SYSCLK crossing the falling edge of 

SYSCLK_N. This differential clock pair should not be asserted until VCCA, VCCIO,

 

VCC33_SM,

 

and

 

VCC (12 V Ararat) are stabilized. 

SYSUTST_REFCLK/

SYSUTST_REFCLK_N

I

These serve as reference clocks for the processor socket logic analyzer interposer 

device during debug. It is not used by the processor, and is not connected internally 

to the die. Electrical specifications on these clocks are identical to SYSCLK/

SYSCLK_N

TCK

I

Test Clock (TCK) provides the clock input for the processor TAP. 

TDI

I

Test Data In (TDI) transfers serial test data into the processor. TDI provides the 

serial input needed for JTAG specification support. 

TDO

O

Test Data Out (TDO) transfers serial test data out of the processor. TDO provides 

the serial output needed for JTAG specification support. 

TESTHI[1]

I

This pin must be tied to 1.1 V using a 50 ohm resistor.

TESTHI[2]

I

This pin must be tied to 1.1 V using a 50 ohm resistor.

TESTHI[4]

I

This pin must be tied to 1.1 V using a 5k ohm resistor.

THERMALERT_N

O

Thermal Alert (THERMALERT_N) is an output signal and is asserted when the on-die 

thermal sensors readings exceed a pre-programmed threshold. 

THERMTRIP_N

O

The processor protects itself from catastrophic overheating by use of an internal 

thermal sensor. Thermal Trip will activate at a temperature that is significantly 

above the maximum case temperature (TCASE) to ensure that there are no false 

trips. Once activated, the processor will stop all execution and the signal remains 

latched until RESET_N goes active. There is no hysteresis built into the thermal 

sensor itself; as long as the die temperature drops below the trip level, a RESET_N 

pulse will reset the processor and execution will continue. If the temperature has 

not dropped below the trip level, the processor will continue to drive THERMTRIP_N 

and remain stopped.

TMS

I

Test Mode Select (TMS) is a JTAG specification support signal used by debug tools.

TRIGGER[1:0]

I

TRIGGER[1:0] pins are needed for XDP connectivity; please refer to 

RS - Boxboro-MC Platform OEM Test and Debug Guide for routing guidelines.

TRST_N

I

Test Reset (TRST_N) resets the TAP logic. TRST_N must be driven electrically low 

during power on Reset. Please refer to RS - Boxboro-MC Platform OEM Test and 

Debug Guide for routing guidelines.

VCC33_SM

I

VCC33_SM is a 3.3 V supply to the processor package, required for the PIROM 

interface on the processor package and also Flash device. This pin must be routed 

to a 3.3 V supply. 

VCCA

I

VCCA provides a +1.8 V isolated power supply to the analog portion of the internal 

PLL’s. Refer to the Intel

 Processor 9300 Series Platform Design Guide for 

routing/decoupling recommendations for VCCA.