Intel 2 Quad Q9505S AT80580AJ0736MG User Manual

28

Datasheet

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS 

input buffers. All of the CMOS and Open Drain signals are required to be asserted/

deasserted for at least eight BCLKs in order for the processor to recognize the proper 

signal state. See 

 for the DC specifications. See 

 for additional 

timing requirements for entering and leaving the low power states. 

The processor DC specifications in this section are defined at the processor core (pads) 

unless otherwise stated. All specifications apply to all frequencies and cache sizes 

unless otherwise stated. 

NOTES:
1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

V

IL

 is defined as the voltage range at a receiving agent that will be interpreted as a logical 

low value.

3.

V

IH

 is defined as the voltage range at a receiving agent that will be interpreted as a logical 

high value.

4.

V

IH

 and V

OH

 may experience excursions above V

TT

. 

5.

The V

TT

 referred to in these specifications is the instantaneous V

TT

.

6.

Leakage to V

SS

 with land held at V

TT

.

7.

Leakage to V

TT

 with land held at 300 mV. 

NOTES:
1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

Measured at V

TT

 * 0.2V.

3.

For Vin between 0 and V

OH

. 

V

IL

Input Low Voltage

-0.10

GTLREF – 0.10

V

2, 5

V

IH

Input High Voltage

GTLREF + 0.10

V

TT 

+ 0.10

V

3, 4, 5

V

OH

Output High Voltage

V

TT 

– 0.10

V

TT

V

4,  5

I

OL

Output Low Current

N/A

V

TT_MAX

 / 

[(R

TT_MIN

) + (2 * R

ON_MIN

)]

A

-

I

LI

Input Leakage 
Current

N/A

± 100

µA

6

I

LO

Output Leakage 
Current

N/A

± 100

µA

7

R

ON

Buffer On Resistance

7.5

11

Ω

V

OL

Output Low Voltage

0

0.20

V

-

I

OL

Output Low Current

16

50

mA

2

I

LO

Output Leakage Current

N/A

± 200

µA

3