Intel X3470 BV80605001905AJ User Manual

Product codes

BV80605001905AJ

Introduction

Datasheet, Volume 1

• Supports the following traffic types to or from the PCH

— DMI -> PCI Express Port 0 write traffic

— DMI -> PCI Express Port 1 write traffic

— DMI -> DRAM

— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)

— Processor core -> DMI

• APIC and MSI interrupt messaging support

— Message Signaled Interrupt (MSI and MSI-X) messages

• Downstream SMI, SCI, and SERR error indication
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port

DMA, floppy drive, and LPC bus masters

• DC coupling – no capacitors between the processor and the PCH
• Polarity inversion
• PCH end-to-end lane reversal across the link
• Supports Half Swing “low-power/low-voltage” and Full Swing “high-power/high-

voltage” modes

1.2.4

Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between
processor and a PECI master, usually the PCH.

1.3

Power Management Support

1.3.1

Processor Core

• Full support of ACPI C-states as implemented by the following processor C-states:

— C0, C1, C1E, C3, C6

• Enhanced Intel SpeedStep

Technology

1.3.2

System

• S0, S1, S4, S5

1.3.3

Memory Controller

• Conditional self-refresh
• Dynamic power-down

1.3.4

PCI Express*

• L0s and L1 ASPM power management capability.

— L0s not supported on the Intel Xeon

processor 3400 series when configured

as PCI Express 4x4