Intel X3470 BV80605001905AJ User Manual
Product codes
BV80605001905AJ
Power Management
40
Datasheet, Volume 1
4.2.4.1
Core C0 State
The normal operating state of a core where code is being executed.
4.2.4.2
Core C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1/C1E) instruction.
MWAIT(C1/C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1/C1E state. See the Intel
state or the C1/C1E state. See the Intel
®
64 and IA-32 Architecture Software
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E, see
threads. For more information on C1E, see
.
4.2.4.3
Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because the
core’s caches are flushed, the processor does not wake any core that is in the C3 state
when either a snoop is detected or when another core accesses cacheable memory.
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because the
core’s caches are flushed, the processor does not wake any core that is in the C3 state
when either a snoop is detected or when another core accesses cacheable memory.
4.2.4.4
Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural
state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero
volts. During exit, the core is powered on and its architectural state is restored.
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural
state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero
volts. During exit, the core is powered on and its architectural state is restored.
4.2.4.5
C-State Auto-Demotion
In general, deeper C-states, such as C6, have long latencies and have higher energy
entry/exit costs. The resulting performance and energy penalties become significant
when the entry/exit frequency of a deeper C-state is high.
entry/exit costs. The resulting performance and energy penalties become significant
when the entry/exit frequency of a deeper C-state is high.
Therefore, incorrect or inefficient usage of deeper C-states may have a negative impact
on power consumption. To increase residency and improve power consumption in
deeper C-states, the processor supports C-state auto-demotion.
on power consumption. To increase residency and improve power consumption in
deeper C-states, the processor supports C-state auto-demotion.
There are two C-State auto-demotion options:
• C6 to C3
• C6/C3 To C1
• C6/C3 To C1
The decision to demote a core from C6 to C3 or C3/C6 to C1 is based on each core’s
residency history. Requests to deeper C-states are demoted to shallower C-states when
the original request doesn't make sense from a performance or energy perspective.
residency history. Requests to deeper C-states are demoted to shallower C-states when
the original request doesn't make sense from a performance or energy perspective.
This feature is disabled by default. BIOS must enable it in the
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.