Intel X3470 BV80605001905AJ User Manual

Datasheet, Volume 1

43

A processor enters the package C3 low power state when: 

• At least one core is in the C3 state.
• The other cores are in a C3 or lower power state, and the processor has been 

granted permission by the platform. 

• The processor has requested the C6 state, but the platform only allowed C3.

In package C3-state, the L3 shared cache is snoopable.

A processor enters the package C6 low power state when:

• At least one core is in the C6 state.
• The other cores are in a C6 state, and the processor has been granted permission 

by the platform.

In package C6 state, all cores save their architectural state and have their core 
voltages reduced. The L3 shared cache is still powered and snoopable in this state. 

The main memory is power managed during normal operation and in low power ACPI 
Cx states.

Any system memory (SM) interface signal that goes to a memory module connector in 
which it is not connected to any actual memory devices (such as, DIMM connector is 
unpopulated, or is single-sided) is tristated. The benefits of disabling unused SM signals 
are:

• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the processor 

I/O buffer receivers caused by reflections from potentially un-terminated 
transmission lines.

When a given rank is not populated, the corresponding chip select and SCKE signals are 
not driven. 

At reset, all rows must be assumed to be populated, until it can be proven that they are 
not populated. This is due to the fact that when CKE is tristated with a DIMM present, 
the DIMM is not ensured to maintain data integrity.