Intel X3470 BV80605001905AJ User Manual

Product codes
BV80605001905AJ
Page of 98
Datasheet, Volume 1
9
Introduction
1
Introduction 
The Intel
®
 Xeon
®
 processor 3400 series are the next generation of 64-bit, multi-core 
processors built on 45-nanometer process technology. Based on the low-power/high-
performance Intel microarchitecture, the processor is designed for a two-chip platform, 
instead of the traditional three-chip platforms (processor, (G)MCH, and ICH). The two-
chip platform consists of a processor and Platform Controller Hub (PCH) and enables 
higher performance, easier validation, and improved x-y footprint. The Intel
®
 3400 
Series Chipset components for servers and workstations are the PCH. The Intel
®
 
Xeon
®
 processor 3400 series is intended for UP server and workstation platforms.
This document provides DC electrical specifications, signal integrity, differential 
signaling specifications, pinout and signal definitions, interface functional descriptions, 
and additional feature information pertinent to the implementation and operation of the 
processor on its respective platform.
Note:
Throughout this document, the Intel
®
 Xeon
®
 processor 3400 series may be referred to 
as “processor”.
Note:
Throughout this document, the Intel
®
 Xeon
®
 processor 3400 series refers to the Intel
®
 
Xeon
®
 X3480, X3470, X3460, X3450, X3440, X3430, and L3426 processors.
Note:
Througout this document, the Intel
®
 3400 Series Chipset Platform Controller Hub may 
be referred to as “PCH”. 
Note:
Some processor features are not available on all platforms. Refer to the processor 
specification update for details.
Included in this family of processors is an integrated memory controller (IMC) and 
integrated I/O (IIO) (such as PCI Express* and DMI) on a single silicon die. This single 
die solution is known as a monolithic processor. For specific features supported on 
individual Intel Xeon processor 3400 series SKUs, refer to the Intel
®
 Xeon
®
 Processor 
3400 Series Specification Update.  
 shows an example server platform block 
diagram.