Intel 9130M NE80567KF0288M User Manual
Product codes
NE80567KF0288M
Intel
®
Itanium
®
Processor 9300 Series Datasheet
105
System Management Bus Interface
6.3
Memory Component Addressing
The Intel Itanium processor 9300 series PIR_A[1:0] pins are used as the memory
address selection signals. The processor does not specify the value on these pins. It is
left to the system architect to set the SMBus memory map. If the processor is the only
device on the bus, these pins may be tied to VSS. PIR_A[2] is tied to VSS internal to
the processor.
address selection signals. The processor does not specify the value on these pins. It is
left to the system architect to set the SMBus memory map. If the processor is the only
device on the bus, these pins may be tied to VSS. PIR_A[2] is tied to VSS internal to
the processor.
Table 6-2.Read Byte SMBus Packet
S
Slave
Address
Write
A
Command
Code
A
S
Slave
Address
Read
A
Data
///
P
1
7-bits
1
1
8-bits
1
1
7-bits
1
1
8-bits
1
1
Table 6-3.Write Byte SMBus Packet
S
Slave
Address
Write
A
Command
Code
A
Data
A
P
1
7-bits
1
1
8-bits
1
8-bits
1
1
Figure 6-1. Intel Itanium Processor 9300 Series Processor Package
VCC33_SM
SM_WP
THERMALERT_N
VCC
A0
A2
SCL
SDA
SPDCLK
SPDDAT
BOOTMODE[1]
SKTID[0]
SKTID[2]
SMBCLK
SMBDAT
AT
34
34
C02C
U2
E
EPRO
M
SPDCLK
SPDDAT
BOOTMODE[1]
SKTID[0]
SKTID[2]
SMBCLK
SMBDAT
VSS
To
P
la
tfo
rm
WP
THERMALERT_N
A1
SKTID[1]
SKTID[1]
BOOTMODE[0]
BOOTMODE[0]
To
P
la
tfo
rm
0.1uF
C5
79
C5
79
PIR_A1
PIR_A0
PIR_A0
PIR_SDA
PIR_SCL
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