Intel 9130M NE80567KF0288M User Manual

33

1.

These parameters are based on design characterization and are not tested.

2.

With 50 termination to VCCIO at the far end. 

V

IH

Input High Voltage

(VCCIO*0.67) + 0.2

VCCIO

V

V

OH

Output High Voltage

VCCIO-0.2

VCCIO

V

V

OL

Output Low Voltage

0

0.25

V

1

I

OL

Output Low Current

16

23

mA

1

I

ILeak

Input Leakage Current

–1000

 200

µA

2

I

OLeak

Output Leakage Current

–1000

 200

µA

1. With 50 termination to VCCIO at the far end.

2. With input leakage current measured at the pin with 0 V and with 1.1 V supplied to the pin. System designers

are advised to check the tolerance of their voltage regulator solutions to ensure a voltage of 1.1 V at the pin.

V

IH

Input High Voltage

(VCCIO*0.67) + 0.2

VCCIO

V

V

IL

Input Low Voltage

0

(VCCIO*0.67) -0.2

V

I

LI

Input Leakage Current

–1000

 200

µA

V

OH

Output High Voltage

VCCIO-0.1

VCCIO

V

1

V

OL

Output Low Voltage

0

0.1

V

1

I

OLeak

Output Leakage Current

–200

 200

µA

1,2

1.

These parameters are not tested and are based on design simulations.

2.

Leakage to VSS with pin held at 1.1 V and leakage to 1.1 V with pin held at VSS.

V

IL

Input Low Voltage

0

(VCCIO*0.67) -0.2

V

1

V

IH

Input High Voltage

(VCCIO*0.67) + 0.2

VCCIO

V

1

V

OL

Output Low Voltage

0

0.25

V

1

I

OL

Output Low Current

16

23

mA

1,2

I

LEAK

Input Leakage Current

–1000

 200

µA

1

I

LO

Output Leakage Current

–1000

 200

µA

1