Intel 9130M NE80567KF0288M User Manual

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All RSVD (RESERVED) pins must be left unconnected. Connection of these pins to 
power, VSS, or to any other signal (including each other) can result in component 
malfunction or incompatibility with future processors. 

For reliable operation, always terminate unused inputs or bi-directional signals to their 
respective deasserted states. A resistor must be used when tying bi-directional signals 
to power or ground, also allowing for system testability. Unused pins of Intel QuickPath 
Interconnect and FB-DIMM ports may be left as no-connects since termination is 
provided on the processor silicon. 

Unused outputs may be terminated on the system board or left connected. Note that 
leaving unused outputs unterminated may interfere with some Test Access Port (TAP) 
functions, complicate debug probing, and prevent boundary scan testing. Signal 
termination for these signal types is discussed in latest revisions of Intel

Processor 9300 Series Platform Design Guide and the Intel

Series Platform Debug Port Design Guide.

Debug pins have ODT and can be left as no-connects. Their routing guidelines are 
provided in the Intel

 Processor 9300 Series Platform Design Guide.

Intel will support mixing CPUs in the same system or hard partition as defined below. A 
hard partition is a smaller system capable of booting an OS, consisting of one or more 
processors, memory and I/O controller hubs that are formed by domain partitioning. 

1. CPUs from adjacent steppings. For example if one cpu is from stepping N, and 

another cpu is from the next stepping, N+1, then CPU

N 

and CPU

N+1 

are compatible. 

Similarly CPU

N 

is not compatible with CPU

N+2

2. If variable frequency mode (VFM) is enabled in one CPU it must be enabled in all 

CPUs. If VFM mode is disabled in one CPU it must be disabled in all CPUs

3. All CPUs in the system or hard partition must have the same core clock speed or 

speed range and the same cache size. 

4. All Intel QPI links must have the same data rate, except for Intel QPI links which 

are disabled or in slow mode. 

5. Core level lockstep (CLL) parts with other CLL parts or the top-bin non-CLL parts 

only.

Intel will not support mixing processors in the same system or hard partition per the 
following:

1. Mixing an enabled VFM part with an fixed frequency mode (FFM) part within the 

same system or hard partition.

The preferred order of voltage sequencing for the  processor is VCC33_SM, 
VccArarat(12 V), VCCA, VCCIO, VCCUNCORE, VCCCORE, and VCCCACHE. The 
processor will not sustain damage if VccArarat(12 V) is applied before VCC33_SM. The 
application of VCC33_SM before VccArarat(12 V) allows the PIROM to be read before 
the processor is powered.

VCC33_SM is brought up first to allow platforms to read the socket Processor 
Information data and the PROCTYPE pin.