Intel 9130M NE80567KF0288M User Manual
Product codes
NE80567KF0288M
Intel
®
Itanium
®
Processor 9300 Series Datasheet
9
Introduction
1
Introduction
1.1
Overview
The Intel
®
Itanium
®
processor 9300 series employs Explicitly Parallel Instruction
Computing (EPIC) design concepts for a tighter coupling between hardware and
software. In this design style, the interface between hardware and software is designed
to enable the software to exploit all available compile-time information, and efficiently
deliver this information to the hardware. It addresses several fundamental performance
bottlenecks in modern computers, such as memory latency, memory address
disambiguation, and control flow dependencies. The EPIC constructs provide powerful
architectural semantics, and enable the software to make global optimizations across a
large scheduling scope, thereby exposing available Instruction Level Parallelism (ILP) to
the hardware. The hardware takes advantage of this enhanced ILP, and provides
abundant execution resources. Additionally, it focuses on dynamic run-time
optimizations to enable the compiled code schedule to flow at high throughput. This
strategy increases the synergy between hardware and software, and leads to greater
overall performance.
software. In this design style, the interface between hardware and software is designed
to enable the software to exploit all available compile-time information, and efficiently
deliver this information to the hardware. It addresses several fundamental performance
bottlenecks in modern computers, such as memory latency, memory address
disambiguation, and control flow dependencies. The EPIC constructs provide powerful
architectural semantics, and enable the software to make global optimizations across a
large scheduling scope, thereby exposing available Instruction Level Parallelism (ILP) to
the hardware. The hardware takes advantage of this enhanced ILP, and provides
abundant execution resources. Additionally, it focuses on dynamic run-time
optimizations to enable the compiled code schedule to flow at high throughput. This
strategy increases the synergy between hardware and software, and leads to greater
overall performance.
The Intel Itanium processor 9300 series consists of up to 4 core processors and a
system interface unit. Each processor core provides a 6-wide, 8-stage deep execution
pipeline. The resources consist of six integer units, six multimedia units, two load and
two store units, three branch units and two floating-point units each capable of
extended, double and single precision arithmetic. The hardware employs dynamic
prefetch, branch prediction, a register scoreboard, and non-blocking caches to optimize
for compile-time non-determinism. Each core provides duplication of all architectural
state to support hardware multithreading thus enabling greater throughput. Three
levels of on-die cache minimize overall memory latency. This includes up to a 24 MB L3
cache, accessed at core speed. The system interface, with its 4 full width and 2 half
width Intel
system interface unit. Each processor core provides a 6-wide, 8-stage deep execution
pipeline. The resources consist of six integer units, six multimedia units, two load and
two store units, three branch units and two floating-point units each capable of
extended, double and single precision arithmetic. The hardware employs dynamic
prefetch, branch prediction, a register scoreboard, and non-blocking caches to optimize
for compile-time non-determinism. Each core provides duplication of all architectural
state to support hardware multithreading thus enabling greater throughput. Three
levels of on-die cache minimize overall memory latency. This includes up to a 24 MB L3
cache, accessed at core speed. The system interface, with its 4 full width and 2 half
width Intel
®
QuickPath Interconnects, enables the processor to directly connect to
other system components, thus can be used as an effective building block for very
large systems. The balanced core and memory subsystem provide high performance
for a wide range of applications ranging from commercial workloads to high
performance technical computing.
large systems. The balanced core and memory subsystem provide high performance
for a wide range of applications ranging from commercial workloads to high
performance technical computing.
The processor will also be socket compatible with the two future Intel Itanium
processors that are currently under development. Organizations will be able to scale
performance and capacity for several years to come through simple and cost-effective
processor upgrades.
processors that are currently under development. Organizations will be able to scale
performance and capacity for several years to come through simple and cost-effective
processor upgrades.
The Intel Itanium processor 9300 series supports a range of computing needs and
configurations from a 2-way to large SMP servers. This document provides the
electrical, mechanical and thermal specifications that must be met when using the Intel
Itanium processor 9300 series processor in your systems.
configurations from a 2-way to large SMP servers. This document provides the
electrical, mechanical and thermal specifications that must be met when using the Intel
Itanium processor 9300 series processor in your systems.
1.2
Processor Abstraction Layer
The Intel Itanium processor 9300 series requires implementation-specific Processor
Abstraction Layer (PAL) firmware. PAL firmware supports processor initialization, error
recovery, and other functionality. It provides a consistent interface to system firmware
and operating systems across processor hardware implementations. The Intel
Abstraction Layer (PAL) firmware. PAL firmware supports processor initialization, error
recovery, and other functionality. It provides a consistent interface to system firmware
and operating systems across processor hardware implementations. The Intel
®