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Intel Itanium 9140M NE80567KF028009 User Manual

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NE80567KF028009
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Page of 108
Dual-Core Intel
®
 Itanium
®
 Processor 9000 and 9100 Series Datasheet
105
Signals Reference
A.1.67
TRDY# (I)
The Target Ready (TRDY#) signal is asserted by the target to indicate that it is ready to 
receive a write or implicit writeback data transfer.
A.1.68
TRST# (I)
The TAP Reset (TRST#) signal is an IEEE 1149.1 compliant TAP support signal used by 
debug tools.
A.1.69
WSNP# (I/O)
The Write Snoop (WSNP#) signal indicates that snooping agents will snoop the memory 
write transaction
A.2
Signal Summaries
 list attributes of the processor output, input, and I/O 
signals.
Table A-12.  Output Signals
Name
Active Level
Clock
Signal Group
CPUPRES#
Low
—
Platform
DBSY_C1#
Low
BCLKp
Data 
DBSY_C2#
Low
BCLKp
Data
DRDY_C1#
Low
BCLKp
Data
DRDY_C2#
Low
BCLKp
Data
FERR#
Low
Asynchronous
PC Compatibility, 
IERR Mode
SBSY_C1#
Low
BCLKp
Data
SBSY_C2#
Low
BCLKp
Data
TDO
High
TCK
TAP
THRMTRIP#
Low
Asynchronous
Error
THRMALERT#
Low
Asynchronous
Error
Table A-13.  Input Signals (Sheet 1 of 2)
Name
Active Level
Clock
Signal Group
Qualified
BPRI#
Low
BCLKp
Arbitration
Always
BR1#
Low
BCLKp
Arbitration
Always
BR2#
Low
BCLKp
Arbitration
Always
BR3#
Low
BCLKp
Arbitration
Always
BCLKp
High
—
Control
Always
BCLKn
High
—
Control
Always
D/C#
Low
BCLKp
System Bus
Request Phase (Mem Rd)
DEFER#
Low
BCLKp
Snoop
Snoop Phase
DHIT#
Low
BCLKp
System Bus
IDS#+1
GSEQ#
Low
BCLKp
Snoop
Snoop Phase