Intel L5238 EU80573JJ0676M Data Sheet
Product codes
EU80573JJ0676M
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications
18
2.4.2
PLL Power Supply
An on-die PLL filter solution is implemented on the Dual-Core Intel® Xeon® Processor
5200 Series. The
5200 Series. The
V
CCPLL
input is used for this configuration in Dual-Core Intel® Xeon®
Processor 5200 Series-based platforms. Please refer to
for DC
specifications. Refer to the appropriate platform design guidelines for decoupling and
routing guidelines.
routing guidelines.
2.5
Voltage Identification (VID)
The Voltage Identification (VID) specification for the Dual-Core Intel® Xeon®
Processor 5200 Series
Processor 5200 Series
is defined by the Voltage Regulator Module (VRM) and Enterprise
Voltage Regulator-Down (EVRD) 11.0 Design Guidelines. The voltage set by the VID
signals is the reference VR output voltage to be delivered to the processor Vcc pins.
VID signals are open drain outputs, which must be pulled up to V
signals is the reference VR output voltage to be delivered to the processor Vcc pins.
VID signals are open drain outputs, which must be pulled up to V
TT
. Please refer to
for the DC specifications for these signals. A voltage range is provided in
and changes with frequency. The specifications have been set such that one
voltage regulator can operate with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core frequency may have different default VID settings. This is
reflected by the VID range values provided in
devices at the same core frequency may have different default VID settings. This is
reflected by the VID range values provided in
.
The Dual-Core Intel® Xeon® Processor 5200 Series
uses six voltage identification
signals, VID[6:1], to support automatic selection of power supply voltages.
specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor
socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply
the voltage that is requested, the voltage regulator must disable itself. See the Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines for further details.
refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor
socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply
the voltage that is requested, the voltage regulator must disable itself. See the Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines for further details.
Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines defines VID[7:0], VID7 and VID0 are not used on the
Dual-Core Intel® Xeon® Processor 5200 Series; VID7 is always hard wired low at the
voltage regulator.
(EVRD) 11.0 Design Guidelines defines VID[7:0], VID7 and VID0 are not used on the
Dual-Core Intel® Xeon® Processor 5200 Series; VID7 is always hard wired low at the
voltage regulator.
Table 2-2.
BSEL[2:0] Frequency Table
BSEL2
BSEL1
BSEL0
Bus Clock Frequency
0
0
0
266.66 MHz
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
333.33 MHz
1
0
1
Reserved
1
1
0
400 MHz
1
1
1
Reserved