Intel 2 Duo T5600 LE80537GF0342M User Manual

Datasheet

19

Extended low power states (C1E, C2E, C3E, C4E) optimize for power by forcibly 

reducing the performance state of the processor when it enters a package low power 

state. Instead of directly transitioning into the package low power state, the extended 

low power state first reduces the performance state of the processor by performing an 

Enhanced Intel SpeedStep Technology transition down to the lowest operating point. 

Upon receiving a break event from the package low power state, control will be 

returned to software while an Enhanced Intel SpeedStep Technology transition up to 

the initial operating point occurs. The advantage of this feature is that it significantly 

reduces leakage while in the package low power states. 

Long-term reliability may not be assured if Extended Low Power States are not 

enabled.

The processor implements two software interfaces for requesting extended package 

low power states: MWAIT instruction extensions with sub-state hints and via BIOS by 

configuring a software programmable MSR to automatically promote package low 

power states to extended package low power states. 

Extended Stop-Grant and Extended Deeper Sleep must be enabled via the BIOS for the 

processor to remain within specification. 

Enhanced Intel SpeedStep Technology transitions are multistep processes that require 

clocked control. These transitions cannot occur when the processor is in the Sleep or 

Deep Sleep package low power states since processor clocks are not active in these 

states. Extended Deeper Sleep is an exception to this rule when the Hard C4E 

configuration is enabled through a software programmable MSR. This Extended Deeper 

Sleep state configuration will lower the core voltage to the Deeper Sleep level while in 

Deeper Sleep and, upon exit, will automatically transition to the lowest operating 

voltage and frequency to reduce snoop service latency. The transition to the lowest 

operating point or back to the original software requested point may not be 

instantaneous. Furthermore, upon very frequent transitions between active and idle 

states, the transitions may lag behind the idle state entry resulting in the processor 

either executing for a longer time at the lowest operating point or running idle at a high 

operating point. Observations and analyses show this behavior should not significantly 

impact total power savings or performance score while providing power benefits in 

most other cases.

The processor incorporates FSB low power enhancements:

• Dynamic FSB Power Down
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On-die Termination disabling
• Low  V

CCP

 (I/O termination voltage)