Intel E7310 LF80565QH0254M Data Sheet
Product codes
LF80565QH0254M
Document Number: 318080-002
53
Electrical Specifications
Figure 2-24. Voltage Sequence Timing Requirements
BCLK
Vcc
PWRGOOD
RESET#
Td
V
TT
Ta
Tb
V
CC_BOOT
Te
V
CCPLL
VID[6:1] / BSEL[2:0]
Ta= T43 (V
CC_BOOT
stable to VID[6:1] / BSEL[2:0] valid)
Tb= T44 (VID[6:1] / BSEL[2:0] valid to Vcc stable)
Tc= T48 (V
Tc= T48 (V
TT
stable to VID[6:1] / BSEL[2:0] valid)
Td= T36 (PWRGOOD assertion to RESET# de-assertion)
Te= T41 (V
Te= T41 (V
CC
stable to PWRGOOD assertion)
Tf = T37 (BCLK stable to PWRGOOD assertion)
Tg = T49 (V
Tg = T49 (V
CCPLL
stable to PWRGOOD assertion)
Th = T45 Reset Configuration Signals (A[35:3]#, BR[1:0]#, INIT#, SMI#) Setup Time
Ti= T46 Reset Configuration Signals (A[35:3]#, INIT#, SMI#) Hold Time
Tj= T47 Reset Configuration Signals (BR[1:0]#) Hold Time
Ti= T46 Reset Configuration Signals (A[35:3]#, INIT#, SMI#) Hold Time
Tj= T47 Reset Configuration Signals (BR[1:0]#) Hold Time
Th
Ti
Tj
Reset Configuration
Signals(A[35:3]#,
INIT#, SMI#)
Reset Configuration
Signals BR[1:0]#
Tc
Tf
Tg