Intel LF80550KF100007 Data Sheet
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
17
Electrical Specifications
2
Electrical Specifications
2.1
Front Side Bus and GTLREF
Most Dual-Core Intel® Xeon® Processor 7100 Series processor front side bus (FSB)
signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This
technology provides improved noise margins and reduced ringing through low voltage
swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up
resistors to provide the high logic level and termination. AGTL+ output buffers differ
from GTL+ buffers with the addition of an active pMOS pull-up transistor to “assist” the
pull-up resistors during the first clock of a low-to-high voltage transition. Platforms
implement a termination voltage level for AGTL+ signals defined as V
signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This
technology provides improved noise margins and reduced ringing through low voltage
swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up
resistors to provide the high logic level and termination. AGTL+ output buffers differ
from GTL+ buffers with the addition of an active pMOS pull-up transistor to “assist” the
pull-up resistors during the first clock of a low-to-high voltage transition. Platforms
implement a termination voltage level for AGTL+ signals defined as V
TT
. Because
platforms implement separate power planes for each processor, separate V
CC
and V
TT
supplies are necessary. This configuration allows for improved noise tolerance as
processor frequency increases. Speed enhancements to data and address busses have
caused signal integrity considerations and platform design methods to become even
more critical than with previous processor families. Design guidelines for the processor
front side bus are detailed in the appropriate platform design guides (refer to
processor frequency increases. Speed enhancements to data and address busses have
caused signal integrity considerations and platform design methods to become even
more critical than with previous processor families. Design guidelines for the processor
front side bus are detailed in the appropriate platform design guides (refer to
The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers
to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see
to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see
for GTLREF specifications). Please refer to the appropriate
platform design guidelines for details. Termination resistors (R
TT
) for AGTL+ signals are
provided on the processor silicon and are terminated to V
TT
. The on-die termination
resistors are a selectable feature and can be enabled or disabled via the ODTEN signal.
For end bus agents, on-die termination resistors are enabled to control reflections on
the transmission line. For the middle bus agent, on-die termination R
For end bus agents, on-die termination resistors are enabled to control reflections on
the transmission line. For the middle bus agent, on-die termination R
TT
resistors must
be disabled. Intel chipsets will also provide on-termination, thus eliminating the need
to terminate the bus on the motherboard for most AGTL+ signals. Processor wired-OR
signals may also include additional on-die resistors (R
to terminate the bus on the motherboard for most AGTL+ signals. Processor wired-OR
signals may also include additional on-die resistors (R
L
) to further ensure proper noise
margin and signal integrity. R
L
is not configurable and is always enabled for these
signals. See
for a list of these signals.
illustrates the active on-die termination.