Intel LF80550KF100007 Data Sheet

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Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

The Processor Information ROM (PIROM) responds to two SMBus packet types: Read 
Byte and Write Byte. However, since the PIROM is write-protected, it will acknowledge a 
Write Byte command but ignore the data. The Scratch EEPROM responds to Read Byte 
and Write Byte commands. 

 diagrams the Read Byte command. 

diagrams the Write Byte command. Following a write cycle to the scratch ROM, 
software must allow a minimum of 10 ms before accessing either ROM of the processor.

In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents 
a read bit, ‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’ 
represents a negative acknowledge (NACK). The shaded bits are transmitted by the 
Processor Information ROM or Scratch EEPROM, and the bits that aren’t shaded are 
transmitted by the SMBus host controller. In the tables, the data addresses indicate 8 
bits. The SMBus host controller should transmit 8 bits with the most significant bit 
indicating which section of the EEPROM is to be addressed: the Processor Information 
ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).

The lower half (128 bytes) of the SMBus memory component is an electrically 
programmed read-only memory with information about the processor. This information 
is permanently write-protected. 

 shows the data fields and 

provides the formats of the data fields included in the Processor Information ROM 
(PIROM).

The PIROM consists of the following sections:

• Header
• Processor Data
• Processor Core Data
• Cache  Data
• Package  Data
• Part Number Data
• Thermal Reference Data
• Feature Data
• Other Data

1

7-bits

1

1

8-bits

1

1

7-bits

1

1

8-bits

1

1

1

7-bits

1

1

8-bits

1

8-bits

1

1