Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
Datasheet
129
Bit Access Default
Value
Description
management section of the BIOS spec.
Bits[1:0] Power
Bits[1:0] Power
state
00: D0 Default
01: D1 Not Supported
10: D2 Not Supported
11: D3
01: D1 Not Supported
10: D2 Not Supported
11: D3
1.9.38
SWSMI - Software SMI
B/D/F/Type: 0/2/0/PCI
Address Offset:
Address Offset:
E0-E1h
Default Value:
0000h
Access:
RW;
Size: 16
bits
As long as there is the potential that DVO port legacy drivers exist which expect this
register at this address, Dev#2F0 address E0h-E1h must be reserved for this register.
register at this address, Dev#2F0 address E0h-E1h must be reserved for this register.
Bit Access Default
Value
Description
15:8 RW 00h Software Scratch Bits (SWSB):
7:1 RW 00h
Software Flag (SWF):
Used to indicate caller and SMI function
desired, as well as return result.
Used to indicate caller and SMI function
desired, as well as return result.
0 RW 0b
CPU Uncore Software SMI Event
(GSSMIE):
When Set this bit will trigger an SMI. Software
must write a "0" to clear this bit.
(GSSMIE):
When Set this bit will trigger an SMI. Software
must write a "0" to clear this bit.