Intel D425 AU80610006252AA User Manual

Datasheet 

 31 

B/D/F/Type: 0/0/0/PCI 

Address Offset: 

2-3h 

Default Value: 

A000h 

Access:  

RO; 

Size: 16 

bits 

This register combined with the Vendor Identification register uniquely identifies any 
PCI device. 

15:0 RO  A000h  Core 

Device Identification Number (DID):  
Identifier assigned to the CPU Uncore 
core/primary PCI device.  
The device IDs for PNV family are: 
A00X: Intel® Atom

TM

 Processor D400 and 

D500 Series for DT 
A01X: Intel® Atom

TM 

Processor N400 

Series for MB 

B/D/F/Type: 0/0/0/PCI 

Address Offset: 

4-5h 

Default Value: 

0006h 

Access: 

 RO; RW; 

Size: 16 

bits 

Since CPU Uncore Device #0 does not physically reside on PCI_A, many of the bits are 

not implemented.

 

15:10 RO 

00h  Core 

9 RO  0b Core 

Fast Back-to-Back Enable (FB2B):  
This bit controls whether or not the master 
can do fast back-to-back write. Since device 
0 is strictly a target this bit is not 
implemented and is hardwired to 0. Writes 
to this bit position have no effect. 

8 RW  0b Core 

SERR Enable (SERRE):  
This bit is a global enable bit for Device 0 
SERR messaging. The CPU Uncore does not 
have an SERR signal. The CPU Uncore 
communicates the SERR condition by 
sending an SERR message over DMI to the 
SouthBridge.  
1: The CPU Uncore is enabled to generate 
SERR messages over DMI for specific Device 
0 error conditions that are individually 
enabled in the ERRCMD and DMIUEMSK