Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
Datasheet
47
1.5.20
PAM2 - Programmable Attribute Map 2
B/D/F/Type: 0/0/0/PCI
Address Offset:
92h
Default Value:
00h
Access:
RO; RW/L;
Size: 8
bits
This register controls the read, write, and shadowing attributes of the BIOS areas
from 0C8000h- 0CFFFFh.
from 0C8000h- 0CFFFFh.
Bit Acces
s
Defau
lt
Value
RST/
PWR
Description
7:6 RO 00b Core
Reserved ()
5:4 RW/L 00b Core
0CC000-0CFFFF Attribute (HIENABLE):
Reserved
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads
are serviced by DMI.
11: Normal DRAM Operation: All reads and writes
are serviced by DRAM.
Reserved
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads
are serviced by DMI.
11: Normal DRAM Operation: All reads and writes
are serviced by DRAM.
3:2 RO 00b Core
Reserved ()
1:0 RW/L 00b Core
0C8000-0CBFFF Attribute (LOENABLE):
This field controls the steering of read and write
cycles that address the BIOS area from 0C8000 to
0CBFFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads
are serviced by DMI.
11: Normal DRAM Operation: All reads and writes
are serviced by DRAM.
This field controls the steering of read and write
cycles that address the BIOS area from 0C8000 to
0CBFFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads
are serviced by DMI.
11: Normal DRAM Operation: All reads and writes
are serviced by DRAM.