Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
8
Datasheet
1
Processor Configuration
Registers
Registers
This is Volume 2 of the Intel® Atom
TM
Processor D400 and D500 Series Datasheet,
and is intended to be distributed as part of the complete document. This document
provides register information for the processor.
1.1
Register Terminology
The following table shows the register-related terminology that is used in this
document.
document.
Item Definition
RO
Read Only bit(s). Writes to these bits have no effect. These are static
values only.
values only.
RO-V
Read Only/Volatile bit(s). Writes to these bits have no effect. These are
status bits only. The value to be read may change based on internal events.
status bits only. The value to be read may change based on internal events.
RO-V-S Read
Only/Volatile/Sticky bit(s). Writes to these bits have no effect.
These are status bits only. The value to be read may change based on
internal events. Bits are not returned to their default values by "warm"
reset, but will be reset with a cold/complete reset.
internal events. Bits are not returned to their default values by "warm"
reset, but will be reset with a cold/complete reset.
AF
Atomic Flag bit(s). The first time the bit is read with an enabled byte, it
returns the value 0, but a side effect of the read is that the value changes to
1. Any subsequent reads with enabled bytes return a 1 until a 1 is written to
the bit. When the bit is read, but the byte is not enabled, the state of the bit
does not change, and the value returned is irrelevant, but will match the
state of the bit.
When a 0 is written to the bit, there is no effect. When a 1 is written to the
bit, its value becomes 0, until the next byte-enabled read. When the bit is
written, but the byte is not enabled, there is no effect.
Conceptually, this is “Read to Set, Write 1 to Clear”
returns the value 0, but a side effect of the read is that the value changes to
1. Any subsequent reads with enabled bytes return a 1 until a 1 is written to
the bit. When the bit is read, but the byte is not enabled, the state of the bit
does not change, and the value returned is irrelevant, but will match the
state of the bit.
When a 0 is written to the bit, there is no effect. When a 1 is written to the
bit, its value becomes 0, until the next byte-enabled read. When the bit is
written, but the byte is not enabled, there is no effect.
Conceptually, this is “Read to Set, Write 1 to Clear”
RW Read/Write
bit(s). These bits can be read and written by software.
Hardware may only change the state of this bit by reset.
RW1C
Read/Write 1 to Clear bit(s). These bits can be read. Internal events
may set this bit. A software write of 1 clears (sets to ‘0’) the corresponding
bit(s) and a write of 0 has no effect.
may set this bit. A software write of 1 clears (sets to ‘0’) the corresponding
bit(s) and a write of 0 has no effect.
RW1C-L-S Read/Write
1
to
Clear/Lockable/Sticky bit(s). These bits can be read.
Internal events may set this bit. A software write of 1 clears (sets to ‘0’) the
corresponding bit(s) and a write of 0 has no effect. Bits are not cleared by
"warm" reset, but will be reset with a cold/complete reset. Additionally there
is a Key bit (which is marked RW-K or RW-L-K) that, when set, prohibits this
bit field from being writeable (bit field becomes Read Only/Volatile).
corresponding bit(s) and a write of 0 has no effect. Bits are not cleared by
"warm" reset, but will be reset with a cold/complete reset. Additionally there
is a Key bit (which is marked RW-K or RW-L-K) that, when set, prohibits this
bit field from being writeable (bit field becomes Read Only/Volatile).