Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
Datasheet
85
1.7.3
DMIPVCCAP2 - DMI Port VC Capability Register 2
B/D/F/Type: 0/0/0/DMIBAR
Address Offset:
8-Bh
Default Value:
00000000h
Access:
RO;
Size: 32
bits
Describes the configuration of PCI Express Virtual Channels associated with this port.
Bit Access Default
Value
RST/
PWR
Description
31:24 RO
00h Core
Reserved for VC Arbitration Table Offset
(RESERVED ())
(RESERVED ())
23:8 RO 0000h Core
Reserved (RESERVED ()
7:0 RO 00h Core
Reserved for VC Arbitration Capability
(VCAC)
(VCAC)
1.7.4
DMIPVCCTL - DMI Port VC Control
B/D/F/Type: 0/0/0/DMIBAR
Address Offset:
C-Dh
Default Value:
0000h
Access:
RO; RW;
Size: 16
bits
Bit Access Default
Value
RST/
PWR
Description
15:4 RO 000h Core
Reserved ()
3:1 RW 000b Core
VC Arbitration Select (VCAS):
This field will be programmed by software to
the only possible value as indicated in the VC
Arbitration Capability field.
The value 000b when written to this field will
indicate the VC arbitration scheme is hardware
fixed (in the root complex). This field cannot be
modified when more than one VC in the LPVC
group is enabled.
000: Hardware fixed arbitration scheme. E.g.
Round Robin
Others: Reserved
See the PCI express specification for more
details
This field will be programmed by software to
the only possible value as indicated in the VC
Arbitration Capability field.
The value 000b when written to this field will
indicate the VC arbitration scheme is hardware
fixed (in the root complex). This field cannot be
modified when more than one VC in the LPVC
group is enabled.
000: Hardware fixed arbitration scheme. E.g.
Round Robin
Others: Reserved
See the PCI express specification for more
details
0 RO 0b Core
Reserved for Load VC Arbitration Table
(RESERVED ())
(RESERVED ())