Intel 2 Duo E7200 AT80571PH0613M Data Sheet
Product codes
AT80571PH0613M
Electrical Specifications
30
Datasheet
2.7.3.2
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
for details on which GTL+ signals do not include on-die
termination.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF.
lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.
NOTES:
1.
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
GTLREF is to be generated from V
TT
by a voltage divider of 1% resistors. If an Adjustable
GTLREF circuit is used on the board (for Quad-Core processors compatibility), the two
GTLREF lands connected to the Adjustable GTLREF circuit require the following:
GTLREF_PU = 50 Ω, GTLREF_PD = 100 Ω.
GTLREF lands connected to the Adjustable GTLREF circuit require the following:
GTLREF_PU = 50 Ω, GTLREF_PD = 100 Ω.
3.
R
TT
is the on-die termination resistance measured at V
TT
/3 of the GTL+ output driver.
4.
COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and
COMP8 resistors are to V
COMP8 resistors are to V
SS
.
Table 15.
GTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
GTLREF_PU
GTLREF_PD
GTLREF pull up on Intel
3 Series Chipset family
boards
3 Series Chipset family
boards
57.6 * 0.99
57.6
57.6 * 1.01
Ω
2
GTLREF pull down on
Intel 3 Series Chipset
family boards
Intel 3 Series Chipset
family boards
100 * 0.99
100
100 * 1.01
Ω
2
R
TT
Termination Resistance
45
50
55
Ω
3
COMP[3:0]
COMP Resistance
49.40
49.90
50.40
Ω
4
COMP8
COMP Resistance
24.65
24.90
25.15
Ω
4