Intel L7555 AT80604004875AA User Manual

38

Intel® Xeon® Processor 7500 Datasheet, Volume 1

VTx-diff-pp-CLK-pin Transmitter differential swing 

using a CLK like pattern

0.9*mi

n(VTx-

diff-pp-

pin)

max(VTxdi

ff-pp-pin)

mV

1

V

Tx-cm-dc-pin

Transmitter output DC common 

mode, defined as average of V

D+

 

and V

D-

0.23

0.27

Fraction of 

V

Tx-diff-pp-pin

3

V

Tx-cm-ac-pin

Transmitter output AC common 

mode, defined as ((V

D+

 + V

D-

)/2 - 

V

Tx-cm-dc-pin

)

-

0.0375

0.0375

Fraction of 

V

Tx-diff-pp-pin

TX

duty-UI-pin

This is computed as absolute 

difference between average value 

of all UI with that of average of 

odd UI, which in magnitude would 

equal absolute difference between 

average of all UI and average of all 

even UI.

0

0.018

UI

TX1UI-Rj-NoXtalk-pin 

Rj value of 1-UI jitter, using setup 

of Figure 2-7. With X-talk off, but 

on-die system like noise present. 

This extraction is to be done after 

software correction of DCD

0

0.008

UI

2

TX1UI-Dj-NoXtalk--pin

pp Dj value of 1-UI jitter With X-

talk off, but on-die system like 

noise present.

-0.01

0.01

UI

2

TXN-UI-Rj-NoXtalkpin

Rj value of N-UI jitter. With X-talk 

off, but on-die system like noise 

present. Here 1 < N < 9.This 

extraction is to be done after 

software correction of DCD

0

0.012

UI

2

TXN-UI-Dj-NoXtalkpin

pp Dj value of N-UI jitter. With X-

talk off, but on-die system like 

noise present. Here 1 < N < 9.Dj 

here indicated Djdd of dual-dirac 

fitting, after software correction of 

DCD

-0.04

0.04

0.2

UI

2

T

Tx-data-clk-skew-pin

Delay of any data lane relative to 

clock lane, as measured at Tx 

output

-0.5

0.5

UI

T

Rx-data-clk-skew-pin

Delay of any data lane relative to 

the clock lane, as measured at the 

end of Tx+ channel. This 

parameter is a collective sum of 

effects of data clock mismatches 

in Tx and on the medium 

connecting Tx and Rx.

-1

4

UI

VRx-CLK 

Forward CLK Rx input voltage 

sensitivity (differential pp)

150

mV

VRx-Vmargin

Any data lane Rx input voltage 

(differential pp) measured at 

BER=1E-9

100

mV

TRx-Tmargin 

Timing width for any data lane 

using repetitive patterns (check 

validation conditions) and clean 

forwarded CLK, measured at 

BER=1E-9

0.8

UI