Intel 2 Duo T9500 EC80576GG0646M User Manual

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Datasheet

• Improved Intel® Thermal Monitor mode:

— When the on-die thermal sensor indicates that the die temperature is too high, 

the processor can automatically perform a transition to a lower frequency and 

voltage specified in a software-programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to 

acceptable levels, an up-transition to the previous frequency and voltage point 

occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions 

enabling better system-level thermal management. 

• Enhanced thermal management features:

— Digital Thermal Sensor and Out of Specification detection
— Intel® Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in 

case of unsuccessful TM2 transition.

— Dual-core thermal management synchronization. 

Each core in the dual processor implements an independent MSR for controlling 

Enhanced Intel SpeedStep Technology, but both cores must operate at the same 

frequency and voltage. The processor has performance state coordination logic to 

resolve frequency and voltage requests from the two cores into a single frequency and 

voltage request for the package as a whole. If both cores request the same frequency 

and voltage, then the processor will transition to the requested common frequency and 

voltage. If the two cores have different frequency and voltage requests, then the 

processor will take the highest of the two frequencies and voltages as the resolved 

request and transition to that frequency and voltage.

The processor also supports Dynamic FSB Frequency Switching and Intel Dynamic 

Acceleration Technology mode on select SKUS. The operating system can take 

advantage of these features and request a lower operating point called SuperLFM (due 

to Dynamic FSB Frequency Switching) and a higher operating point Intel Dynamic 

Acceleration Technology mode. 

Extended low-power states (C1E, C2E, C3E, C4E, C6E) optimize for power by forcibly 

reducing the performance state of the processor when it enters a package low-power 

state. Instead of directly transitioning into the package low-power state, the enhanced 

package low-power state first reduces the performance state of the processor by 

performing an Enhanced Intel SpeedStep Technology transition down to the lowest 

operating point. Upon receiving a break event from the package low-power state, 

control will be returned to software while an Enhanced Intel SpeedStep Technology 

transition up to the initial operating point occurs. The advantage of this feature is that it 

significantly reduces leakage while in low-power states. 

C6 is always enabled in the extended low-power state, as described above.

Long-term reliability cannot be assured unless all the extended low power states are 

enabled.

The processor implements two software interfaces for requesting extended package 

low-power states: MWAIT instruction extensions with sub-state hints and via BIOS by 

configuring IA32_MISC_ENABLES MSR bits to automatically promote package low-

power states to extended package low-power states.