Intel AT80604005280AA User Manual
Intel® Xeon® Processor 7500 Datasheet, Volume 1
147
Features
7
Features
7.1
Introduction
The Intel® Xeon® processor 7500 series package includes PECI 2.0, TAP and SMBus
interfaces which allow access to processor’s package information. The processor die is
connected to the PECI2.0 and TAP, and these interfaces can be used for access to the
configuration registers of the processor. The processor Information ROM (PIROM) and
scratch EEROM, are accessed via the SMBus connection.
interfaces which allow access to processor’s package information. The processor die is
connected to the PECI2.0 and TAP, and these interfaces can be used for access to the
configuration registers of the processor. The processor Information ROM (PIROM) and
scratch EEROM, are accessed via the SMBus connection.
Note:
Actual implementation may vary. This figure is provided to offer a general understanding of the
architecture.
Figure 7-1. Logical Schematic of Intel® Xeon® Processor 7500 Series Package
V
CC33
SM_WP
XXT
H
R
MAL
ER
T_N
VC
C
A0
A2
SC
L
SDA
X
X
SPDC
L
K
XX
SPD
DA
T
XXS
KT
ID
[0]
XXS
KT
ID[2
]
S2
S4
D2
D3
EEPROM
SPDC
L
K
SPDD
A
T
SK
T
ID
[0
]
SMBCLK
SMBDA
T
Package Pins
WP
VCCIOF
=1
.1V
THER
MAL
ERT_
N
A1
XXS
KT
ID
[1]
SK
T
ID
[1]
VCCA
VCCB
B1
B2
CPU
Die
SK
TID[2]
S3
D4
S1
D1
GND
PCA9509
GTL2003
SRE
F
GR
E
F
GN
D
EN
34C02
Level Shifter
Level Shifter
A2
A1
GND