Intel AT80604005280AA User Manual
Features
164
Intel® Xeon® Processor 7500 Datasheet, Volume 1
7.5.4.10
RES4: Reserved 4
This location is reserved. Writes to this register have no effect.
7.5.4.11
L2SIZE: L2 Cache Size
This location contains the size of the level-two cache in kilobytes. Writes to this register
have no effect. Data format is decimal.
have no effect. Data format is decimal.
Example: The Intel® Xeon® processor 7500 series has a 2 MB L2 cache. Thus, offset
3Fh-40h will contain a value of 0800h.
3Fh-40h will contain a value of 0800h.
7.5.4.12
L3SIZE: L3 Cache Size
This location contains the size of the level-three cache in kilobytes. Writes to this
register have no effect. Data format is decimal.
register have no effect. Data format is decimal.
Example: The Intel® Xeon® processor 7500 series has a 24 MB L3 cache. Thus, offset
41h-42h will contain a value of 6000h.
41h-42h will contain a value of 6000h.
7.5.4.13
CVID: Cache Voltage ID
This field contains the voltage requested via the CVID pins. This field is in mV and is
reflected in binary coded decimal. Some systems read this offset to determine if all
processors support the same default CVID setting. Writes to this register have no
effect.
reflected in binary coded decimal. Some systems read this offset to determine if all
processors support the same default CVID setting. Writes to this register have no
effect.
Example: A voltage of 1.350 V CVID would contain an Offset 43-44h value of 1350h.
Offset:
3Ah
Bit
Description
7:0
Core Voltage Tolerance, Low
00h-FFh: mV
Offset:
3Bh-3Eh
Bit
Description
31:0
RESERVED
00000000h-FFFFFFFFh: Reserved
Offset:
3Fh-40h
Bit
Description
15:0
L2 Cache Size
0000h-FFFFh: KB
Offset:
41h-42h
Bit
Description
15:0
L3 Cache Size
0000h-FFFFh: KB