Intel AT80604005280AA User Manual

Intel® Xeon® Processor 7500 Series Datasheet, Volume 1

Introduction

ALL INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE.

The Intel

Xeon

processor 7500 series is a next-generation Intel

Xeon

family

multi-core MP processor. The processor uses Intel

QuickPath Interconnect Technology,

implementing up to four high-speed serial point-to-point links. It is optimized for MP
configurations targeted at enterprise and technical computing applications, delivering
server-class RAS and performance.

The Intel® Xeon® Processor 7500 Series Datasheet, Volume 1 provides DC and AC
electrical specifications, differential signaling specifications, pinout and signal
definitions, package mechanical specifications and thermal requirements, and
additional features pertinent to implementation and operation of the Intel

Xeon

processor 7500 series.

Intel

Xeon

processor 7500 series are multi-core processors, based on 45-nm

process technology. The processor features Intel

QuickPath Interconnect point-to-

point links capable of up to 6.4 GT/s, up to 24 MB of shared cache, and an integrated
memory controller. The processors support all the existing Streaming SIMD Extensions
2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD Extensions 4
(SSE4). The processors support several Advanced Technologies: Execute Disable Bit,
Intel

64 Technology, Enhanced Intel Speedstep

Technology, Intel

Virtualization

Technology (Intel

VT), and Simultaneous Multi Threading.

1.1

Terminology

A ‘_N’ after a signal name refers to an active low signal, indicating that a signal is in the
asserted state when driven to a low level. For example, when RESET_N is low (that is,
when RESET_N is asserted), a reset has been requested. Conversely, when TCK is high
(that is, when TCK is asserted), a test clock request has occurred.

• DDR3 — Double Data Rate 3 synchronous dynamic random access memory

(SDRAM) is the name of the new DDR memory standard that is being developed as
the successor to DDR2 SDRAM.

• Enhanced Intel SpeedStep

Technology — Enhanced Intel SpeedStep

Technology allows the O/S to reduce power consumption when performance is not
needed.

• Eye Definitions — The eye at any point along the data channel is defined to be the

creation of overlapping of a large number of UI of the data signal and timing width

Feature

Intel® Xeon® Processor 7500 Series

Cache Sizes

Instruction Cache (L1) = 32 KB/core (I) and16 KB/core (D)

Data Cache (L2) = 256KB/core
Last Level Cache (L3) = up to 24MB shared among cores

Data Transfer Rate

Up to four full-width Intel® QuickPath Interconnect links, up to 6.4

GT/s in each direction

Multi-Core Support

Up to 8 cores per processor

Multiple Processor Support

Up to 8 processors in a two hop topology. Up to 4 processors directly

connected to each other.

Package

1567-land FCLGA