Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Processor Integrated I/O (IIO) Configuration Registers
104
Datasheet, Volume 2
3.4.2.12
INTLIN—Interrupt Line Register
The Interrupt Line register is used to communicate interrupt line routing information
between initialization code and the device driver
between initialization code and the device driver
.
3.4.2.13
INTPIN—Interrupt Pin Register
Indicates what INTx message a device generates. This register has no meaning for
Device 8.
Device 8.
3.4.3
Common Extended Configuration Space Registers
3.4.3.1
CAPID—PCI Express
®
Capability List Register
The PCI Express Capability List register enumerates the PCI Express Capability
structure in the PCI 3.0 configuration space.
structure in the PCI 3.0 configuration space.
Register: INTLIN
Device:
8
Function:
0-2
Offset:
3Ch
Bit
Attr
Default
Description
7:0
RO 00h
Interrupt Line
This bit is RW for devices that can generate a legacy INTx message and is
This bit is RW for devices that can generate a legacy INTx message and is
needed only for compatibility purposes.
Register: INTPIN
Device: 8
Function:
0-2
Offset:
3Dh
Bit
Attr
Default
Description
7:0
RO
00h
Interrupt Pin
These bits have no meaning for the device called out in this section and are
These bits have no meaning for the device called out in this section and are
hard coded to 0.
Device:
8
Function:
0, 1, 2
Offset:
40h
Bit
Attr
Default
Description
7:0
RO
10h
Capability ID
Defines the PCI Express capability ID. 10h is defined as a “PCI Express”
Defines the PCI Express capability ID. 10h is defined as a “PCI Express”
capability.