Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Processor Integrated I/O (IIO) Configuration Registers
126
Datasheet, Volume 2
3.4.4.31
VTISOCHCTRL—Intel VT-d Isoch Related Control Register
3.4.4.32
VTGENCTRL2—Intel VT-d General Control 2 Register
Register:
VTISOCHCTRL
Device:
8
Function:
0
Offset: 188h
Bit
Attr
Default
Description
31:5
RV
0
Reserved
4:2
RWL
0
Number of Isoch cache entries when Isoch Intel VT-d engine is enabled:
000 = 0 entries
001 = 1 entry
010 = 2 entries
Others = Reserved
000 = 0 entries
001 = 1 entry
010 = 2 entries
Others = Reserved
1
RWL
0
2 entries for isochronous Desc
This field may be locked as RO in Intel
This field may be locked as RO in Intel
TXT mode
0
RWL
1
Steer isochronous to non-isochronous Intel VT-d engine
This field may be locked as RO in Intel
This field may be locked as RO in Intel
TXT mode
Register:
VTGENCTRL2
Device:
8
Function:
0
Offset: 18Ch
Bit
Attr
Default
Description
31:11
RV
0
Reserved
10:7
RWL
Fh
LRU Timer
6:5
RWL
01
Prefetch Control
This field controls which Intel VT-d reads are to be considered for
This field controls which Intel VT-d reads are to be considered for
prefetch/snarf/reuse in the Intel
QuickPath Interconnect buffers.
00 = Prefetch/snarf/reuse is disabled.
01 = Prefetch/snarf/reuse is enabled for all leaf/non-leaf Intel VT-d page
01 = Prefetch/snarf/reuse is enabled for all leaf/non-leaf Intel VT-d page
walk reads.
Others = Reserved
4
RV
0
Reserved
3
RV
0
Reserved
2
RV
0
Reserved
1
RV
0
Reserved
0
RV
0
Reserved