Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
129
Processor Integrated I/O (IIO) Configuration Registers
3.4.5.8
CWR[4:7]—Conditional Write Registers 4-7
3.4.5.9
CWR[8:11]—Conditional Write Registers 8-11
3.4.5.10
CWR[12:15]—Conditional Write Registers 12-15
Register:
CWR[4:7]
Device:
8
Function:
1
Offset:
0ECh-0F8h by 4
Bit
Attr
Default
Description
31:0
RWSLB
0h
Conditional Write
These registers are physically mapped to scratch pad registers. A read from
These registers are physically mapped to scratch pad registers. A read from
CWR[n] reads SR[n]. A write to CWR[n] writes SR[n] if SR[n][0] = 0 before the
write, and has no effect otherwise. The registers provide firmware with
synchronization variables (semaphores) that are overloaded onto the same
physical registers as SR.
Register:
CWR[8:11]
Device:
8
Function:
1
Offset:
0FCh, 104h -10Ch by 4
Bit
Attr
Default
Description
31:0
RWLB
0h
Conditional Write
These registers are physically mapped to scratch pad registers. A read from
These registers are physically mapped to scratch pad registers. A read from
CWR[n] reads SR[n]. A write to CWR[n] writes SR[n] if SR[n][0] = 0 before the
write, and has no effect otherwise. The registers provide firmware with
synchronization variables (semaphores) that are overloaded onto the same
physical registers as SR.
Register:
CWR[12:15]
Device:
8
Function:
1
Offset:
110h-11Ch by 4
Bit
Attr
Default
Description
31:0
RWLB
0h
Conditional Write
These registers are physically mapped to scratch pad registers. A read from
These registers are physically mapped to scratch pad registers. A read from
CWR[n] reads SR[n]. A write to CWR[n] writes SR[n] if SR[n][0] = 0 before the
write, and has no effect otherwise. The registers provide firmware with
synchronization variables (semaphores) that are overloaded onto the same
physical registers as SR.