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Intel Xeon L3406 CM80616005010AA User Manual

Product codes
CM80616005010AA
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Processor Integrated I/O (IIO) Configuration Registers
180
Datasheet, Volume 2
3.7.2.1
QPIPCTRL0—Intel
®
 QuickPath Interconnect Protocol Control 0
Register can only be modified under system quiescence. All RWL bits are locked with 
the lock1 bit.
3.7.2.2
QPIPISOCRES—Intel
®
 QuickPath Interconnect Protocol 
Isochronous Reservation
Controls how TID are allocated to for Isochronous requests. Values applies across all 
TID allocation pools for a given Intel QuickPath Interconnect port.
Register modified only under system quiescence.
Register:
 QPIPCTRL0
Device:
 16
Function:
 1
Offset:
 4Ch
Bit
Attr
Default
Description
31:30
RWL
0
VC1 Priority
When Isoc is enabled this value should is expected to be set as Critical.
00 = Standard
01 = Reserved
10 = High
11 = Critical (recommended when isoc enabled)
29:28
RWL
0
VCp Priority
When Isoc is enabled this value should is expected to be set as High (‘10).
00 = Standard
01 = Reserved
10 = High (recommended when isoc enabled)
11 = Critical
27:0
RWL
0
Reserved
Register:
 QPIPISOCRES
Device:
 16
Function:
 1
Offset:
 B8h
Bit
Attr
Default
Description
31:17
RV
0
Reserved
16
RW
0
Isoc Enabled
When set the VCp and VC1 Isoc flows are enabled on Intel QuickPath 
Interconnect. It is required when this is enabled that the “VC1 Maximum” and 
the “VCp Maximum” values be non-zero.
15:12
RW
0
VC1 Reserved 
Number of TIDs that are reserved for VC1 (Azalia) Traffic. The value must be 
less then “MaxRequest minus the Reserved for High priority”. Should be set no 
greater than the “VC1 Maximum” value. 
0–7 = Invalid values
>7 = Reserved
Recommend setting (VC1) = 3