Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
217
Processor Uncore Configuration Registers
4.5.12
SAD_INTERLEAVE_LIST_0; SAD_INTERLEAVE_LIST_1
SAD_INTERLEAVE_LIST_2; SAD_INTERLEAVE_LIST_3
SAD_INTERLEAVE_LIST_4; SAD_INTERLEAVE_LIST_5
SAD_INTERLEAVE_LIST_6; SAD_INTERLEAVE_LIST_7
This register contains SAD DRAM package assignments. When the corresponding
DRAM_RULE hits, a 3-bit number (determined by mode) is used to index into the
interleave_list to determine which package is the HOME for this address.
DRAM_RULE hits, a 3-bit number (determined by mode) is used to index into the
interleave_list to determine which package is the HOME for this address.
00 = IIH
01 = Socket 0
10 = Reserved
11 = Reserved
01 = Socket 0
10 = Reserved
11 = Reserved
Device:
0
Function:
1
Offset:
C0h, C4h, C8h, CCh, D0h, D4h, D8h, DCh
Access as a DWord
Bit
Attr
Default
Description
31:30
RO
0
Reserved
29:28
RW
0
PACKAGE7. Package for group 7 of interleaves.
27:26
RO
0
Reserved
25:24
RW
0
PACKAGE6. Package for group 6 of interleaves.
23:22
RO
0
Reserved
21:20
RW
0
PACKAGE5. Package for group 5 of interleaves.
19:18
RO
0
Reserved
17:16
RW
0
PACKAGE4. Package for group 4 of interleaves.
15:14
RO
0
Reserved
13:12
RW
0
PACKAGE3. Package for group 3 of interleaves.
11:10
RO
0
Reserved
9:8
RW
0
PACKAGE2. Package for group 2 of interleaves.
7:6
RO
0
Reserved
5:4
RW
0
PACKAGE1. Package for group 1 of interleaves.
3:2
RO
0
Reserved
1:0
RW
0
PACKAGE0. Package for group 0 of interleaves.