Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Processor Uncore Configuration Registers
220
Datasheet, Volume 2
4.7
Integrated Memory Controller Control Registers
4.7.1
MC_CONTROL
Primary control register.
Device:
3
Function:
0
Offset:
48h
Access as a DWord
Bit
Attr
Default
Description
31:8
RO
0
Reserved
9
RW
0
CHANNEL1_ACTIVE
When set, this bit indicates MC channel 1 is active. This bit is controlled
When set, this bit indicates MC channel 1 is active. This bit is controlled
(set/reset) by software only. This bit is required to be set for any active
channel when INIT_DONE is set by software.
8
RW
0
CHANNEL0_ACTIVE
When set, this bit indicate MC channel 0 is active. This bit is controlled
When set, this bit indicate MC channel 0 is active. This bit is controlled
(set/reset) by software only. This bit is required to be set for any active
channel when INIT_DONE is set by software.
7
WO
0
INIT_DONE
MC initialize complete signal. Setting this bit will exit the training mode of
MC initialize complete signal. Setting this bit will exit the training mode of
the Integrated Memory Controller and begin normal operation including all
enabled maintenance operations. Any CHANNNEL_ACTIVE bits not set
when writing a 1 to INIT_DONE will cause the corresponding channel to be
disabled.
6
RW
0
DIVBY3EN. Divide By 3 Enable
When set, MAD would use the longer pipeline for transactions that are 3-
When set, MAD would use the longer pipeline for transactions that are 3-
or 6-way interleaved and shorter pipeline for all other transactions. The
SAG registers must be appropriately programmed as well.
5
RO
0
Reserved
4
RW
0
CHANNELRESET1
Reset only the state within the channel. Equivalent to pulling warm reset
Reset only the state within the channel. Equivalent to pulling warm reset
for that channel.
3
RW
0
CHANNELRESET0
Reset only the state within the channel. Equivalent to pulling warm reset
Reset only the state within the channel. Equivalent to pulling warm reset
for that channel.
2
RW
0
AUTOPRECHARGE. Autoprecharge Enable
This bit should be set with the closed page bit. If it is not set with closed
This bit should be set with the closed page bit. If it is not set with closed
page, address decode will be done without setting the autoprecharge bit.
1
RW
0
ECCEN. ECC Checking enables. When this bit is set in lockstep mode the
ECC checking is for the x8 SDDC. ECCEN without Lockstep enables the x4
SDDC ECC checking.
0
RW
0
CLOSED_PAGE
When set, the MC supports a Closed Page policy. The default is Open Page
When set, the MC supports a Closed Page policy. The default is Open Page
but BIOS should always configure this bit.