Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
227
Processor Uncore Configuration Registers
4.8
TAD—Target Address Decoder Registers
4.8.1
TAD_DRAM_RULE_0; TAD_DRAM_RULE_1
TAD_DRAM_RULE_2; TAD_DRAM_RULE_3
TAD_DRAM_RULE_4; TAD_DRAM_RULE_5
TAD_DRAM_RULE_6; TAD_DRAM_RULE_7
TAD DRAM rules. Address map for channel determination within a package. All
addresses sent to this HOME agent must hit a valid enabled DRAM_RULE. No error will
be generated if they do not and memory aliasing will happen.
addresses sent to this HOME agent must hit a valid enabled DRAM_RULE. No error will
be generated if they do not and memory aliasing will happen.
Device:
3
Function:
1
Offset:
80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch
Access as a DWord
Bit
Attr
Default
Description
31:20
RO
0
Reserved
19:6
RW
-
LIMIT. DRAM rule top limit address
This field must be strictly greater than previous rule, even if this rule is
This field must be strictly greater than previous rule, even if this rule is
disabled, unless this rule and all following rules are disabled. Lower limit is
the previous rule (or 0 if it is the first rule).
5:3
RO
0
Reserved
2:1
RW
-
MODE. DRAM rule interleave mode
If a DRAM_RULE hits, a 3-bit number is used to index into the corresponding
If a DRAM_RULE hits, a 3-bit number is used to index into the corresponding
interleave_list to determine which channel the DRAM belongs to. This mode
selects how that number is computed.
00 = Address bits {8,7,6}.
01 = Address bits {8,7,6} XORed with {18,17,16}.
10 = Address bit {6}, MOD3(Address[39..6]). (Note 6 is the high order bit)
11 = reserved.
00 = Address bits {8,7,6}.
01 = Address bits {8,7,6} XORed with {18,17,16}.
10 = Address bit {6}, MOD3(Address[39..6]). (Note 6 is the high order bit)
11 = reserved.
0
RW
0
ENABLE. Enable for DRAM rule