Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
231
Processor Uncore Configuration Registers
The mask and halt bits are defined as shown in
There are 3 registers defined for Padscan usage.
A read operation is performed by writing the index (Chain length — Offset +38 —
length of section +1) of the section to be read and read bit into the control register. The
appropriate scan chain is selected in the scan chain select register. The read is
complete when the read bit in the control register is cleared by the Integrated Memory
Controller. The control register must be read after the read (write) command is issued
to guarantee the read (write) command completes.
length of section +1) of the section to be read and read bit into the control register. The
appropriate scan chain is selected in the scan chain select register. The read is
complete when the read bit in the control register is cleared by the Integrated Memory
Controller. The control register must be read after the read (write) command is issued
to guarantee the read (write) command completes.
When the read data is complete the contents of the data register will be valid. Note that
reads will provide a total of 32 bits which may include adjacent sections of the scan
chain. For example if section 18 which has 11 bits is read out, the data register will
return section 18 in the lower portion of the 32-bit data register along with data from
adjacent sections 9 and 1 in the scan chain. The index in this case would be 5271
(5261 – 18 +38 – 11 +1). Refer to
reads will provide a total of 32 bits which may include adjacent sections of the scan
chain. For example if section 18 which has 11 bits is read out, the data register will
return section 18 in the lower portion of the 32-bit data register along with data from
adjacent sections 9 and 1 in the scan chain. The index in this case would be 5271
(5261 – 18 +38 – 11 +1). Refer to
Table 4-20. Halt and Mask Bit Usage
Mask
Halt
Function
0
X
Serial data is not loaded into the shadow register
1
0
Serial data is loaded into shadow register but will be overwritten
1
1
Serial data is loaded into shadow register and held until halt is cleared. This is
the most commonly used setting.
Table 4-21. Padscan Registers
Register Name
Description
MC_TEST_EP_SCCTL
Scan chain control register
MC_TEST_EP_SCD
Scan chain data register
MC_TEST_LTRCON
Scan chain select register
Figure 4-1. Padscan Accessibility Mechanism
Data Register
32 bit Payload
Control Register
Rd Wr
Index[29:0]
FSM
Shift, Capture, Update, Reset
Pad Scan Chain
Tdi
Tdo
L
S
B
M
S
B
L
S
B
M
S
B
Index
Index 0
Index n
Shadow
Register