Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Processor Uncore Configuration Registers
244
Datasheet, Volume 2
4.10.8
MC_CHANNEL_0_MRS_VALUE_2
MC_CHANNEL_1_MRS_VALUE_2
The initial MRS register values for MR2. This register also contains the values used for
RC0 and RC2 writes for registered DIMMs. These values are used during the automated
training sequence when MRS writes or registered DIMM RC writes are used. The RC
fields do not need to be programmed if the address inversion and 3T/1T transitions are
disabled.
RC0 and RC2 writes for registered DIMMs. These values are used during the automated
training sequence when MRS writes or registered DIMM RC writes are used. The RC
fields do not need to be programmed if the address inversion and 3T/1T transitions are
disabled.
Device:
4, 5
Function:
0
Offset:
74h
Access as a DWord
Bit
Attr
Default
Description
31:24
RO
0
Reserved
23:20
RW
0
RC2
The values to write to the RC2 register on RDIMMs. This value will be
The values to write to the RC2 register on RDIMMs. This value will be
written whenever 3T or 1T timings are enabled by hardware. For this
reason, bit 1 of the RC2 field (bit 21 of this register) will be controlled by
hardware. [23:22] and [20] will be driven with the RDIMM register write
command for RC2.
19:16
RW
0
RC0
The values to write to the RC0 register on RDIMMS. This value will be
The values to write to the RC0 register on RDIMMS. This value will be
written whenever address inversion is enabled or disabled by hardware.
For this reason, bit 0 of the RC0 field (bit 16 of this register) will be
controlled by hardware. [19:17] will be driven with the RDIMM register
write command for RC0.
15:0
RW
0
MR2
The values to write to MR2 for A15:A0.
The values to write to MR2 for A15:A0.