Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
251
Processor Uncore Configuration Registers
4.10.15 MC_CHANNEL_0_ZQ_TIMING
MC_CHANNEL_1_ZQ_TIMING
This register contains parameters that specify ZQ timing. All units are DCLK unless
otherwise specified. The register encodings are specified where applicable.
otherwise specified. The register encodings are specified where applicable.
4.10.16 MC_CHANNEL_0_RCOMP_PARAMS
MC_CHANNEL_1_RCOMP_PARAMS
This register contains parameters that specify Rcomp timings.
Device:
4, 5
Function:
0
Offset:
94h
Access as a DWord
Bit
Attr
Default
Description
31
RO
0
Reserved
30
RW
1
Parallel_ZQ
Enable ZQ calibration to different ranks in parallel.
Enable ZQ calibration to different ranks in parallel.
29
RW
1
tZQenable
Enable the issuing of periodic ZQCS calibration commands.
Enable the issuing of periodic ZQCS calibration commands.
28:8
RW
16410
ZQ_Interval
Nominal interval between periodic ZQ calibration in increments of tREFI.
Nominal interval between periodic ZQ calibration in increments of tREFI.
7:5
RW
4
tZQCS
Specifies ZQCS cycles in increments of 16. This is the minimum delay
Specifies ZQCS cycles in increments of 16. This is the minimum delay
between ZQCS and any other command. This register should be
programmed to at least 64/16=4='100' to conform to the DDR3
specification.
4:0
RW
0
tZQInit
Specifies ZQInit cycles in increments of 32. This is the minimum delay
Specifies ZQInit cycles in increments of 32. This is the minimum delay
between ZQCL and any other command. This register should be
programmed to at least 512/32=16='10000' to conform to the DDR3
specification.
Device:
4, 5
Function:
0
Offset:
98h
Access as a DWord
Bit
Attr
Default
Description
31:17
RO
0
Reserved
16
RW
0
RCOMP_EN. Enable Rcomp
When set, the Integrated Memory Controller will do the programmed blocking
When set, the Integrated Memory Controller will do the programmed blocking
of requests and send indications.
15:10
RW
2
RCOMP_CMD_DCLK
Delay from the start of an RCOMP command blocking period in which the
Delay from the start of an RCOMP command blocking period in which the
command rcomp update is done. Program this field to 15 for all
configurations.
9:4
RW
9
RCOMP_LENGTH
Number of Dclks during which all commands are blocked for an RCOMP
Number of Dclks during which all commands are blocked for an RCOMP
update. Data RCOMP update is done on the last DCLK of this period. Program
this field to 31 for all configurations.
3:0
RW
0
RCOMP_INTERVAL
Duration of interval between Rcomp in increments of tRefI. Register value is
Duration of interval between Rcomp in increments of tRefI. Register value is
tRefI–1. For example a setting of 0 will produce an interval of tRefI.