Intel Xeon L3406 CM80616005010AA User Manual

262

Datasheet, Volume 2

This register can be set to match memory address on a per channel basis. This match is 
used for ECC and Address parity error injection. The Match address is specified in this 
register and address fields can be masked in the Mask bits. Any mask bits set to 1 will 
always match. To match all addresses, all of the mask bits can be set to 1.

The MC_CHANNEL_X_ECC_ERROR_INJECT register can be used to set the trigger for 
the error injection.

63:42

RO

0

41

RW

0

MASK_DIMM
If set to 1, ignore DIMM address during address comparison.

40

RW

0

MASK_RANK
If set to 1, ignore RANK address during address comparison.

39

RW

0

MASK_BANK
If set to 1, ignore BANK address during address comparison.

38

RW

0

MASK_PAGE
If set to 1, ignore PAGE address during address comparison.

37

RW

0

MASK_COL
If set to 1, ignore COLUMN address during address comparison.

36

RW

0

DIMM
DIMM address for 1 or 2DPC. For 3DPC, bits 36 and 35 represent the DIMM 

address and bit 34 represent the RANK address.

35:34

RW

0

RANK
Rank address for 1 or 2DPC. For 3DPC, bits 36 and 35 represent the DIMM 

address and bit 34 represent the RANK address.

33:30

RW

0

BANK
Bank address.

29:14

RW

0

PAGE
Page address.

13:0

RW

0

COLUMN
Column address.