Intel Xeon L3406 CM80616005010AA User Manual

Product codes
CM80616005010AA
Page of 302
Processor Uncore Configuration Registers
266
Datasheet, Volume 2
4.11.3
MC_SAG_CH0_0; MC_SAG_CH0_1; MC_SAG_CH0_2; 
MC_SAG_CH0_3; MC_SAG_CH0_4; MC_SAG_CH0_5; 
MC_SAG_CH0_6; MC_SAG_CH0_7
Channel Segment Address Registers. For each of the 8 interleave ranges, they specify 
the offset between the System Address and the Memory Address and the System 
Address bits used for level 1 interleave, which should not be translated to Memory 
Address bits. Memory Address is calculated from System Address and the contents of 
these registers by the following algorithm:
m[39:16] = SystemAddress[39:16] - (2’s complement {Offset[23:0]});
m[15:6] = SystemAddress[15:6];
If (Removed[2]) {Bit 8 removed};
If (Removed[1]) {Bit 7 removed};
If (Removed[0]) {Bit 6 removed};
MemoryAddress[36:6] = m[36:6];
Removed Div3 Interleave
000 0 None
001 0 2-way 
011 0 4-way
000 1 3-way
001 1 6-way
All other combinations are not supported.
Device:
4
Function:
1
Offset:
80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch
Access as a DWord
Bit
Attr
Default
Description
31:28
RO
0
Reserved
27
RW
0
DIVBY3
This bit indicates the rule is a 3 or 6 way interleave.
26:24
RW
0
REMOVED
These are the bits to be removed after offset subtraction. These bits 
correspond to System Address [8,7,6].
23:0
RW
0
OFFSET
This value should be subtracted from the current system address to create a 
contiguous address space within a channel. BITS 9:0 ARE RESERVED AND 
MUST ALWAYS BE SET TO 0.