Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
System Address Map
282
Datasheet, Volume 2
The VGA memory address range can also be mapped to system memory in SMM. IIO is
totally transparent to the workings of this region in the SMM mode. All outbound and
inbound accesses to this address range are always forwarded to the VGA device by the
IIO. Refer to
totally transparent to the workings of this region in the SMM mode. All outbound and
inbound accesses to this address range are always forwarded to the VGA device by the
IIO. Refer to
for further details of inbound and outbound VGA
decoding.
5.2.3.2
C/D/E/F Segments
The E/F region is used for BIOS flash in the early stages of the boot flow and could be
mapped to any firmware hub port in IA32 system. E/F could also be used to address
DRAM from an I/O device (processors have registers to select between addressing
BIOS flash and DRAM). IIO does not explicitly decode the E/F region in the outbound
direction and relies on subtractive decoding to forward accesses to this region to the
legacy PCH through DMI. IIO does not explicitly decode inbound accesses to the E/F
address region. It is expected that the DRAM low range that IIO decodes will be setup
to cover the E/F address range. By virtue of that, IIO will forward inbound accesses to
the E/F segment to system DRAM.
mapped to any firmware hub port in IA32 system. E/F could also be used to address
DRAM from an I/O device (processors have registers to select between addressing
BIOS flash and DRAM). IIO does not explicitly decode the E/F region in the outbound
direction and relies on subtractive decoding to forward accesses to this region to the
legacy PCH through DMI. IIO does not explicitly decode inbound accesses to the E/F
address region. It is expected that the DRAM low range that IIO decodes will be setup
to cover the E/F address range. By virtue of that, IIO will forward inbound accesses to
the E/F segment to system DRAM.
If it is necessary to block inbound access to these
ranges, a Generic Memory Protection Ranges could be used.
C/D region is used in system DRAM memory for BIOS and option ROM shadowing. IIO
does not explicitly decode these regions for inbound accesses. Software must program
one of the system DRAM memory decode ranges that IIO uses (for inbound system
memory decoding) to include these ranges. If it is necessary to block inbound access to
these ranges, the Generic Memory Protection Ranges could be used.
does not explicitly decode these regions for inbound accesses. Software must program
one of the system DRAM memory decode ranges that IIO uses (for inbound system
memory decoding) to include these ranges. If it is necessary to block inbound access to
these ranges, the Generic Memory Protection Ranges could be used.
All outbound accesses to the C-F regions are first positively decoded against all valid
targets’ address ranges and if none match, these address are forwarded to the
subtractive decode port of the IIO.
targets’ address ranges and if none match, these address are forwarded to the
subtractive decode port of the IIO.
IIO will complete locks to this range, but cannot guarantee atomicity when writes and
reads are mapped to separate destinations.
reads are mapped to separate destinations.
5.2.4
Address Region between 1 MB and TOLM
Note:
The ME stolen memory space must be located below Top Of Low Memory
(TOLM) (or TOHM ifit needs to be above 4 GB).
This region is always allocated to system DRAM memory. Software must set up one of
the coarse memory decode ranges that IIO uses (for inbound system memory
decoding) to include this address range. By virtue of that, IIO will forward inbound
accesses to this region to system memory (unless any of these access addresses fall
within a protected DRAM range as described in
the coarse memory decode ranges that IIO uses (for inbound system memory
decoding) to include this address range. By virtue of that, IIO will forward inbound
accesses to this region to system memory (unless any of these access addresses fall
within a protected DRAM range as described in
). It would be an error for
IIO to receive outbound accesses to an address in this region, other than snoop
requests, from Intel QuickPath Interconnect, but IIO does not explicitly check for this
error condition but would rather forward such accesses to the subtractive decode port
by virtue of subtractive decoding.
requests, from Intel QuickPath Interconnect, but IIO does not explicitly check for this
error condition but would rather forward such accesses to the subtractive decode port
by virtue of subtractive decoding.
Any inbound access that decodes to be within one of the two coarse memory decode
windows but has no real DRAM populated for that address, will result in a master abort
response on PCI Express.
windows but has no real DRAM populated for that address, will result in a master abort
response on PCI Express.